always @ (posedge CLK or negedge SD_RST)//计数器Count,最大为2的22次方。
begin
if(!SD_RST)
begin
Count<=23'd0;
end
else
Count <= Count + 23'd1 ;
end
//assign led_clk = Count[22] ;
always @(posedge CLK or negedge SD_RST)
begin
if(!SD_RST)
begin
FPGA_TEST[4] = 0;
end
else
begin
FPGA_TEST[4] = Count[22] ;
end
end
/* always @(posedge led_clk )
begin
if(FPGA_TEST[4]) begin
FPGA_TEST[4] = 0;
end
else if (!FPGA_TEST[4]) begin
FPGA_TEST[4] = 1;
end
end*/
reg kc_en;
/*always @(M_KCIO or SD_RST)
begin
if(!SD_RST)
begin
kc_en = 0;
end
else if ( M_KCIO != 8'b0 ) // kc_en在M_KCIO != 8'b0 情况下为1
begin
kc_en = 1;
end
end*/
always @(posedge CLK or negedge SD_RST)
begin
if(!SD_RST)
begin
kc_en=0;
end
else if(M_KCIO!=8'b0)
begin
kc_en=1;
end
end
always @(posedge CLK or negedge SD_RST)
begin
if(!SD_RST)
begin
F_KC=0;
end
else if( FPGA_KCEN)
begin
F_KC = M_KCIO;
end
else
begin
F_KC = F_KC;
end
end
/*always @( FPGA_KCEN or M_KCIO or SD_RST)
begin
if(!SD_RST)
begin
F_KC = 8'b0;
end
else if ( FPGA_KCEN)
begin
F_KC = M_KCIO;
end
else
begin
F_KC = F_KC;
end
end*/
always @(posedge CLK or negedge SD_RST)
begin
if(!SD_RST)
begin
M_KIIO[8:1] = 8'b0;
FPGA_TEST[3:1] =3'b0;
end
else if( FPGA_KIEN[1])
begin
M_KIIO[8:1] = F_KIN[8:1] ;
FPGA_TEST[3:1] = FPGA_KIEN;
end
else if ( FPGA_KIEN[2])
begin
M_KIIO[8:1] = F_KIN[16:9] ;
FPGA_TEST[3:1] = FPGA_KIEN;
end
else if ( FPGA_KIEN[3])
begin
M_KIIO[1] = F_KIN[17];
M_KIIO[2] = F_KIN[18];
M_KIIO[3] = F_KIN[19];
M_KIIO[4] = DYIN[1];
M_KIIO[5] = DYIN[2];
M_KIIO[6] = DYIN[3];
M_KIIO[7] = DYIN[4];
M_KIIO[8] = 0;
FPGA_TEST[3:1] = FPGA_KIEN;
end
else
begin
M_KIIO[8:1] = 8'bz;
FPGA_TEST[3:1] = 3'bz;
end
end
endmodule