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module crc5_test(clock,key,sdata,rdata,crc,dload,rst_n,led,seg,dig);
input clock; //系统时钟(48MHz)
input[4:0] key; //按键输入(KEY1~KEY5)
output[11:0]sdata; //3位16进制数输出(在数码管1~3显示)
input[11:0]rdata; //3位16进制数输入(在数码管6~8显示)
input[4:0]crc; //crc冗余码输入
output dload; //加载信号输出
output rst_n; //复位信号输出
output[1:0]led; //LED输出指示
output[7:0]seg; //数码管段码输出
output[7:0]dig; //数码管位码输出
reg[11:0]sdata_r;
reg[7:0]seg_r;
reg[7:0]dig_r;
reg dload_r;
reg[16:0]count; //时钟分频计数器
reg[4:0]dout1,dout2,dout3; //消抖寄存器
reg[4:0]buff; //边沿检测寄存器
reg[2:0]cnt3; //数码管扫描计数器
reg[3:0]disp_dat; //数码管扫描显存
reg div_clk; //分频时钟,用于消抖和扫描
wire[4:0]key_edge; //按键消抖输出
//信号输出
assign seg = seg_r;
assign dig = dig_r;
assign sdata = sdata_r;
assign dload = dload_r;
assign led = {~dload_r,rst_n};
//时钟分频部分
always @(posedge clock)
begin
if (count < 17'd120000)
begin
count <= count + 1'b1;
div_clk <= 1'b0;
end
else
begin
count <= 17'd0;
div_clk <= 1'b1;
end
end
//按键消抖部分
always @(posedge clock)
begin
if(div_clk)
begin
dout1 <= key;
dout2 <= dout1;
dout3 <= dout2;
end
end
//按键边沿检测部分
always @(posedge clock)
begin
buff <= dout1 | dout2 | dout3;
end
//下降沿检测
assign key_edge = ~(dout1 | dout2 | dout3) & buff;
//3位16进制数输出部分
always @(posedge clock) //按键1
begin
if(key_edge[0]) //下降沿检测
sdata_r[11:8] <= sdata_r[11:8] + 1'b1;
end
always @(posedge clock) //按键2
begin
if(key_edge[1]) //下降沿检测
sdata_r[7:4] <= sdata_r[7:4] + 1'b1;
end
always @(posedge clock) //按键3
begin
if(key_edge[2]) //下降沿检测
sdata_r[3:0] <= sdata_r[3:0] + 1'b1;
end
always @(posedge clock) //按键4
begin
if(key_edge[3]) //下降沿检测
dload_r <= ~dload_r;
end
assign rst_n = buff[4]; //按键5
//数码管扫描显示部分
always @(posedge clock) //定义上升沿触发进程
begin
if(div_clk)
cnt3 <= cnt3 + 1'b1;
end
always @(posedge clock)
begin
if(div_clk)
begin
case(cnt3) //选择扫描显示数据
3'd0:disp_dat = sdata_r[11:8]; //第一个数码管
3'd1:disp_dat = sdata_r[7:4]; //第二个数码管
3'd2:disp_dat = sdata_r[3:0]; //第三个数码管
3'd3:disp_dat = rdata[11:8]; //第四个数码管
3'd4:disp_dat = rdata[7:4]; //第五个数码管
3'd5:disp_dat = rdata[3:0]; //第六个数码管
3'd6:disp_dat = {3'd0,crc[4]}; //第七个数码管
3'd7:disp_dat = crc[3:0]; //第八个数码管
endcase
case(cnt3) //选择数码管显示位
3'd0:dig_r = 8'b01111111; //选择第一个数码管显示
3'd1:dig_r = 8'b10111111; //选择第二个数码管显示
3'd2:dig_r = 8'b11011111; //选择第三个数码管显示
3'd3:dig_r = 8'b11101111; //选择第四个数码管显示
3'd4:dig_r = 8'b11110111; //选择第五个数码管显示
3'd5:dig_r = 8'b11111011; //选择第六个数码管显示
3'd6:dig_r = 8'b11111101; //选择第七个数码管显示
3'd7:dig_r = 8'b11111110; //选择第八个数码管显示
endcase
end
end
always @(disp_dat)
begin
case(disp_dat) //七段译码
4'h0:seg_r = 8'hc0; //显示0
4'h1:seg_r = 8'hf9; //显示1
4'h2:seg_r = 8'ha4; //显示2
4'h3:seg_r = 8'hb0; //显示3
4'h4:seg_r = 8'h99; //显示4
4'h5:seg_r = 8'h92; //显示5
4'h6:seg_r = 8'h82; //显示6
4'h7:seg_r = 8'hf8; //显示7
4'h8:seg_r = 8'h80; //显示8
4'h9:seg_r = 8'h90; //显示9
4'ha:seg_r = 8'h88; //显示a
4'hb:seg_r = 8'h83; //显示b
4'hc:seg_r = 8'hc6; //显示c
4'hd:seg_r = 8'ha1; //显示d
4'he:seg_r = 8'h86; //显示e
4'hf:seg_r = 8'h8e; //显示f
endcase
end
endmodule
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