FPGA做AD采样？

喜鹊王子

FPGA做AD采样？ [复制链接]

AD芯片的时序图应该抓住哪些关键时间参数啊？我看给的时间参数很多，应该不是每个参数都要管吧？

白丁

参考一下这个吧

module AD_R(clk,sck,Din,nRST,pulse,CNV,Dout,done,flag);
input clk,sck,nRST,Din,pulse;
output CNV,done,flag;
output [15:0]Dout;
reg done,CNV,flag;
reg [15:0]Dout;

wire neg_sck;
reg temp1,temp2;

always@(posedge clk or negedge nRST)
begin
if(~nRST)
begin
      temp1 <= 1'b0;
      temp2 <= 1'b0;
end

else
begin
      temp1 <= sck;
      temp2 <= temp1;
end
end
assign neg_sck = (!temp1)&(temp2);

wire pos_sck;
reg temp3,temp4;

always@(posedge clk or negedge nRST)
begin
if(~nRST)
begin
      temp3 <= 1'b0;
      temp4 <= 1'b0;
end

else
begin
      temp3 <= sck;
      temp4 <= temp3;
end
end
assign pos_sck = (temp3)&(!temp4);

wire pos_pulse;
reg temp5,temp6;

always@(posedge clk or negedge nRST)
begin
if(~nRST)
begin
      temp5 <= 1'b0;
      temp6 <= 1'b0;
end

else
begin
      temp5 <= pulse;
      temp6 <= temp5;
end
end
assign pos_pulse = (temp5)&(!temp6);

reg ena_cnt_read;
reg rst_cnt_read;
reg[4:0] bit_cnt_read;
always @(posedge clk or negedge nRST )
begin
      if(~nRST)
         bit_cnt_read <=5'b0;
      else if(ena_cnt_read)
         bit_cnt_read <=bit_cnt_read +5'b1;
      else if(rst_cnt_read)
         bit_cnt_read <= 5'b0;
end

reg ena_cnt_wait;
reg [8:0] bit_cnt_wait;
always @(posedge clk or negedge nRST)
if(~nRST) bit_cnt_wait<= 0;
else if(ena_cnt_wait) bit_cnt_wait <= bit_cnt_wait +1;
else bit_cnt_wait <= 0;

reg [4:0]state,next_state;
parameter x_idle       = 5'b00001;
parameter x_wait       = 5'b00010;
parameter x_read_D15_1  = 5'b00100;
parameter x_read_D15_2  = 5'b01000;
parameter x_read       = 5'b10000;

parameter wait_time_1 = 9'd125;
parameter wait_time_2 = 9'd3;
parameter read_time = 5'd14;

always @(posedge clk or negedge nRST)
if(~nRST) state <= x_idle;
else state <= next_state;

always @(state or pos_pulse or neg_sck or bit_cnt_read or bit_cnt_wait)
begin
      next_state    = state;
      ena_cnt_read = 1'b0;
      ena_cnt_wait = 1'b0;
      rst_cnt_read = 1'b0;
      done          = 1'b0;



      case(state)

      x_idle:
         if(pos_pulse)
         begin
            //flag = 1'b1;
            CNV = 1'b1;
            //nCS = 1'b1;
            rst_cnt_read = 1'b1;
            next_state = x_wait;
         end
         else
         begin
            //flag = 1'b0;
            CNV = 1'b0;
            //nCS = 1'b1;
            //next_state = x_idle;
         end

      x_wait:
         if(bit_cnt_wait == wait_time_1)
            begin
            next_state = x_read_D15_1;
            CNV = 1'b0;
            end
         else
            begin
                  next_state = x_wait;
                  ena_cnt_wait = 1'b1;
            end

      x_read_D15_1:
         if(bit_cnt_wait == wait_time_2)
            begin
                  next_state = x_read;
                  Dout[15] = Din;
            end
         else
            begin
                  next_state = x_read_D15_1;
                  ena_cnt_wait = 1'b1;
            end



      x_read:
         if(neg_sck)
            begin
                  if(bit_cnt_read > read_time)
                  begin
                     rst_cnt_read = 1'b1;
                     done = 1'b1;
                     next_state = x_idle;
                  end

                  else
                  begin
                     case(bit_cnt_read)

                     5'd0:
                     begin
                     Dout[14]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd1:
                     begin
                     Dout[13]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd2:
                     begin
                     Dout[12]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd3:
                     begin
                     Dout[11]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd4:
                     begin
                     Dout[10]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd5:
                     begin
                     Dout[9]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd6:
                     begin
                     Dout[8]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd7:
                     begin
                     Dout[7]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd8:
                     begin
                     Dout[6]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd9:
                     begin
                     Dout[5]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd10:
                     begin
                     Dout[4]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd11:
                     begin
                     Dout[3]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd12:
                     begin
                     Dout[2]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd13:
                     begin
                     Dout[1]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     5'd14:
                     begin
                     Dout[0]    = Din;
                     ena_cnt_read = 1'b1;
                     end

                     /*5'h15:
                     begin
                     ena_cnt_read = 1'b1;
                     end*/




                     default next_state = x_idle;
                     endcase
                  end
            end

         default next_state = x_idle;
      endcase
end
endmodule