求助！！波形延时复制出现问题。

yekeyaopei

求助！！波形延时复制出现问题。 [复制链接]

麻烦大家问个棘手的问题，代码是根据CP输入信号分频，输出PCI1_CLK和PCI2_CLK，已经分频的间隔时间。PCI2_CLK是PCI1_CLK的延时复制。
为什么PCI2_CLK仿真出来和示波器打出来波形都不对。麻烦哪位高手 解救下。

module bmq (
  clk,rst_n,bmq20_int,cp,time_dir_20,pci1_clk,pci2_clk
   
);
input clk; //时钟信号，50MHz
input rst_n; //复位信号，低电平有效
input cp;   //编码器输入
output pci1_clk;  //输入采集卡1方波
output [31:0] time_dir_20; //输出间隔20个编码器方波时间
output bmq20_int; // 给串口发送触发
output pci2_clk;  //输出采集卡2方波
reg  cp_rx0,cp_rx1; //接收数据寄存器，滤波用
wire cp_rx;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
   cp_rx0 <= 1'b0;
   cp_rx1 <= 1'b0;
  end
else begin
   cp_rx0 <= cp;
   cp_rx1 <= cp_rx0;
  end
end
assign cp_rx =cp_rx1 ^ cp_rx0;
reg out_int;
reg out_int1;
assign bmq20_int= out_int;
reg [4:0] bmq_count;
reg  [39:0] time_20_inc;
reg[31:0] time_dir_20;
reg[39:0] time_dir_20_3;
reg[39:0] time_dir_20_buf;
parameter delay_time=  500000 ;
reg pci2_int;
reg [3:0] num_delay_2;
wire pci2_clk;
always @ (posedge cp_rx or negedge rst_n) begin
if(!rst_n) begin
   bmq_count <=5'h0;
   time_dir_20 <= 32'h0;
   out_int <=1'h0;
   out_int1<=1'h0;
  end
  else begin
  if(time_20_inc - time_dir_20_3 > 40'h1dcd6500) begin     //这部分代码是为了速度很小很小，编码器间隔时间过长，不发送间隔时间及触发采集
     time_dir_20 <= 32'h0;
     time_dir_20_buf <= 40'h0;
     time_dir_20_3 <= time_20_inc;
    bmq_count <=5'h0;
   end         
   else if(bmq_count==20) begin
    out_int <=~out_int;
    out_int1=~out_int1;
    bmq_count <=5'h1;      
    time_dir_20_3 <= time_20_inc;      //时间间隔取32位
   time_dir_20_buf <= time_20_inc -time_dir_20_3;
    time_dir_20 <=time_dir_20_buf[31:0];   
   end else
   bmq_count <= bmq_count+1'h1;
  end
end
assign pci1_clk=out_int  ;

always@ (posedge clk or negedge rst_n) begin
if(!rst_n) time_20_inc <= 40'h0;
else  
        if(bmq_count)
   time_20_inc <= time_20_inc +1'h1;
end
////////////////////////以下代码是PCI2采集卡，是PCI1采集卡触发波形的延时复制
//取了10个寄存器 设计成一个环形队列，每次延时值是固定的，所以延时比较的寄存器都是从队头到队尾 循环比较。
reg out_int2;
always@ (posedge clk or negedge rst_n)  begin
if(!rst_n) out_int2<=1'h0  ;
else out_int2<= out_int1;
end
wire neg_pci2_int1;
assign neg_pci2_int1 =out_int2^out_int1;
reg[39:0] delay_count_1;
reg[39:0] delay_count_2;
reg[39:0] delay_count_3;
reg[39:0] delay_count_4;
reg[39:0] delay_count_5;
reg[39:0] delay_count_6;
reg[39:0] delay_count_7;
reg[39:0] delay_count_8;
reg[39:0] delay_count_9;
reg[39:0] delay_count_10;
reg [3:0] num_delay;
always @ (posedge neg_pci2_int1 or negedge rst_n) begin
  if(!rst_n) begin
            delay_count_1 <= 40'h0;
     delay_count_2 <= 40'h0;
     delay_count_3 <= 40'h0;
     delay_count_4 <= 40'h0;
     delay_count_5 <= 40'h0;
     delay_count_6 <= 40'h0;
     delay_count_7 <= 40'h0;
     delay_count_8 <= 40'h0;
     delay_count_9 <= 40'h0;
     delay_count_10 <= 40'h0;
     num_delay <= 4'h0;
     end
    else begin  
      case (num_delay)
        4'd0:   begin delay_count_1 <= time_20_inc; num_delay <=4'h1; end
        4'd1:  begin delay_count_2 <= time_20_inc; num_delay <=4'h2; end
        4'd2:  begin delay_count_3 <= time_20_inc; num_delay <=4'h3; end
        4'd3:  begin delay_count_4 <= time_20_inc; num_delay <=4'h4; end
        4'd4:  begin delay_count_5 <= time_20_inc; num_delay <=4'h5; end
        4'd5:  begin delay_count_6 <= time_20_inc; num_delay <=4'h6; end
        4'd6:  begin delay_count_7 <= time_20_inc; num_delay <=4'h7; end
        4'd7: begin delay_count_8 <= time_20_inc; num_delay <=4'h8; end
        4'd8:  begin delay_count_9 <= time_20_inc; num_delay <=4'h9; end
        4'd9: begin delay_count_10 <= time_20_inc; num_delay <=4'h0; end
        default: num_delay <= 1'h0;
        endcase
    end
end  
reg [39:0] time_20_inc_1;
always@ (posedge clk or negedge rst_n)  begin
   if(!rst_n) begin
    num_delay_2 <= 4'h0;
    pci2_int <=1'h0;
    time_20_inc_1 <=40'h0;
   end else begin
     time_20_inc_1 <=time_20_inc;
    case (num_delay_2)
        4'd0:  if (time_20_inc_1 - delay_count_1 == delay_time) begin
                 num_delay_2 <= 4'h1;
           pci2_int<= ~pci2_int;
          end else pci2_int<= pci2_int;
        4'd1:   if (time_20_inc_1 - delay_count_2 ==delay_time ) begin
                 num_delay_2 <= 4'h2;
          pci2_int<= ~pci2_int;
          end else pci2_int<= pci2_int;
        4'd2:   if (time_20_inc_1 -delay_count_3 == delay_time ) begin
                num_delay_2 <= 4'h3;
           pci2_int<= ~pci2_int;
          end else pci2_int<= pci2_int;
        4'd3:   if (time_20_inc_1 -delay_count_4 == delay_time ) begin
                num_delay_2 <= 4'h4;
           pci2_int<= ~pci2_int;
          end else pci2_int<= pci2_int;
        4'd4:   if (time_20_inc_1 -delay_count_5==delay_time ) begin
                num_delay_2 <= 4'h5;
           pci2_int<= ~pci2_int;
          end else pci2_int<= pci2_int;
        4'd5:   if (time_20_inc_1 -delay_count_6 ==delay_time ) begin
                num_delay_2 <= 4'h6;
           pci2_int<= ~pci2_int;
          end else pci2_int<= pci2_int;
        4'd6:   if (time_20_inc_1 -delay_count_7==delay_time ) begin
                num_delay_2 <= 4'h7;
          pci2_int<= ~pci2_int;
          end else pci2_int<= pci2_int;
        4'd7:  if (time_20_inc_1 -delay_count_8 == delay_time ) begin
                num_delay_2 <= 4'h8;
          pci2_int<= ~pci2_int;
          end else pci2_int<= pci2_int;
        4'd8:   if (time_20_inc_1 -delay_count_9 == delay_time )begin
                num_delay_2 <= 4'h9;
          pci2_int<= ~pci2_int;
          end else pci2_int<= pci2_int;
        4'd9:  if (time_20_inc_1 -delay_count_10 == delay_time ) begin
                num_delay_2 <= 4'h0;
          pci2_int<= ~pci2_int;
          end else pci2_int<= pci2_int;
       default: pci2_int<= 1'b0;
      endcase  
   end
end
assign pci2_clk = pci2_int;
endmodule

yekeyaopei

没有热心的高手吗？

kdy

这位同学，刚看到你的提问，
1、首先仿真不对情况下基本就不用考虑示波器了
2、没有图啊，看完问题后我没理解你在问什么？
3、最后给个实用点的建议：
time_20_inc_1 - delay_count_1 == delay_time
这种宽位数的减法器少用，HDL不是C，这样的写法不止会降低速度，也会导致错误，至少现在你还不熟悉熟了后再用。尽量改成比较器形式。
最后能把问题描述清晰一些吗？
哪怕直接写文字要求。不用代码

[ 本帖最后由 kdy 于 2013-6-24 20:55 编辑 ]