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module TEST_DPRAM(clk,outA);
input clk;
output wire [7:0] outA;
wire [7:0] dpraminaddr;
wire [7:0] dpramindata;
wire [7:0] ramoutdataA;
wire WrEn;
// wire clken;
// assign clken = ~clk;
assign WrEn = (count == 3) ? clk : 0;
assign dpraminaddr = addrin;
assign dpramindata = datain;
assign outA = ramoutdataA;
integer count = 0;
always @(posedge clk)
begin
if(count == 3)
begin
count <= 3;
end
else
begin
count <= count + 1;
end
end
reg [7:0] addrin = 0;
always @(posedge clk)
begin
if(addrin == 255)
begin
addrin <= 0;
end
else
begin
addrin <= addrin + 1;
end
end
reg [7:0] datain = 0;
always @(posedge clk)
begin
if(datain == 255)
begin
datain <= 0;
end
else
begin
datain <= datain + 1;
end
end
GSR GSR_INST (.GSR(1'b1));
PUR PUR_INST (.PUR(1'b1));
RAM_DP RAM_DP_BLOCK(.Clock(clk), .ClockEn(1'b1), .Reset(1'b0),
.WE(clk), .Address(addrin), .Data(datain), .Q(ramoutdataA));
/* DPRAM DPRAM_BLOCK(.DataInA(datain), .DataInB(datain), .AddressA(addrin),
.AddressB(addrin),.ClockA(clken), .ClockB(clken),
.ClockEnA(1'b1), .ClockEnB(1'b1), .WrA(WrEn), .WrB(WrEn),
.ResetA(1'b0), .ResetB(1'b0), .QA(ramoutdataA), .QB(ramoutdataB));*/
endmodule |
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