c2000 开发板要自己接晶振不？要接多大的啊？

xjjxjj897

c2000 开发板要自己接晶振不？要接多大的啊？ [复制链接]

c2000 开发板要自己接晶振不？要接多大的啊？   菜鸟刚开始学。。。请大师指教

qinkaiabc

有片内振荡器60Mhz

常见泽1

有片内哦 亲

xjjxjj897

那最大能工作到多少Mhz？

xjjxjj897

那最大能工作到多少Mhz？

qinkaiabc

1. /*-----------------------------------------------------------------------------
   
2.       Specify the PLL control register (PLLCR) and divide select (DIVSEL) value.
   
3. -----------------------------------------------------------------------------*/
   
4. 
   
5. //#define DSP28_DIVSEL   0 // Enable /4 for SYSCLKOUT
   
6. //#define DSP28_DIVSEL   1 // Disable /4 for SYSCKOUT
   
7. #define DSP28_DIVSEL   2 // Enable /2 for SYSCLKOUT
   
8. //#define DSP28_DIVSEL   3 // Enable /1 for SYSCLKOUT
   
9. 
   
10. 
    
11. #define DSP28_PLLCR   12    // Uncomment for 60 MHz devices [60 MHz = (10MHz * 12)/2]
    
12. //#define DSP28_PLLCR   11
    
13. //#define DSP28_PLLCR   10      // Uncomment for 50 Mhz devices [50 Mhz = (10MHz * 10)/2]
    
14. //#define DSP28_PLLCR    9
    
15. //#define DSP28_PLLCR    8      // Uncomment for 40 MHz devices [40 MHz = (10MHz * 8)/2]
    
16. //#define DSP28_PLLCR    7
    
17. //#define DSP28_PLLCR    6
    
18. //#define DSP28_PLLCR    5
    
19. //#define DSP28_PLLCR    4
    
20. //#define DSP28_PLLCR    3
    
21. //#define DSP28_PLLCR    2
    
22. //#define DSP28_PLLCR    1
    
23. //#define DSP28_PLLCR    0  // PLL is bypassed in this mode
    
24. //----------------------------------------------------------------------------
    
25. 
    
26. /*-----------------------------------------------------------------------------
    
27.       Specify the clock rate of the CPU (SYSCLKOUT) in nS.
    
28. 
    
29.       Take into account the input clock frequency and the PLL multiplier
    
30.       selected in step 1.
    
31. 
    
32.       Use one of the values provided, or define your own.
    
33.       The trailing L is required tells the compiler to treat
    
34.       the number as a 64-bit value.
    
35. 
    
36.       Only one statement should be uncommented.
    
37. 
    
38.       Example 1: 40 MHz devices:
    
39.                  CLKIN is a 10 MHz crystal or internal 10 MHz oscillator
    
40. 
    
41.                  In step 1 the user specified PLLCR = 0x8 for a
    
42.                  40 MHz CPU clock (SYSCLKOUT = 40 MHz).
    
43. 
    
44.                  In this case, the CPU_RATE will be 25.000L
    
45.                  Uncomment the line: #define CPU_RATE 25.000L
    
46. 
    
47.       Example 1: 50 MHz devices:
    
48.                  CLKIN is a 10 MHz crystal or internal 10 MHz oscillator
    
49. 
    
50.                  In step 1 the user specified PLLCR = 0xA for a
    
51.                  50 MHz CPU clock (SYSCLKOUT = 50 MHz).
    
52. 
    
53.                  In this case, the CPU_RATE will be 20.000L
    
54.                  Uncomment the line: #define CPU_RATE 20.000L
    
55. 
    
56. 
    
57.       Example 2: 60 MHz devices:
    
58.                  CLKIN is a 10 MHz crystal or internal 10 MHz oscillator
    
59. 
    
60.                  In step 1 the user specified PLLCR = 0xC for a
    
61.                  60 MHz CPU clock (SYSCLKOUT = 60 MHz).
    
62. 
    
63.                  In this case, the CPU_RATE will be 16.667L
    
64.                  Uncomment the line: #define CPU_RATE 16.667L
    
65. 
    
66. -----------------------------------------------------------------------------*/

复制代码

xjjxjj897

//Select the internal oscillator 1 as the clock source
    CLK_setOscSrc(myClk, CLK_OscSrc_Internal);
   
    // Setup the PLL for x10 /2 which will yield 50Mhz = 10Mhz * 10 / 2
    PLL_setup(myPll, PLL_Multiplier_10, PLL_DivideSelect_ClkIn_by_2);

这样设置但 XCLKOUT为12.5MHz？？？