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【求伪代码或C】以下的decode函数是ARM汇编，只求大致的意思，谢谢
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- .text:00000A58 EXPORT decode
- .text:00000A58 decode ; CODE XREF: com_aes_decryptMy+3Ap
- .text:00000A58 ; .text:00001270p
- .text:00000A58
- .text:00000A58 var_2C = -0x2C
- .text:00000A58
- .text:00000A58 PUSH {R4-R7,LR} ; Push registers
- .text:00000A5A MOV R7, R11 ; Rd = Op2
- .text:00000A5C MOV R6, R10 ; Rd = Op2
- .text:00000A5E MOV R5, R9 ; Rd = Op2
- .text:00000A60 MOV R4, R8 ; Rd = Op2
- .text:00000A62 PUSH {R4-R7} ; Push registers
- .text:00000A64 SUB SP, SP, #0xC ; Rd = Op1 - Op2
- .text:00000A66 MOV R11, R1 ; Rd = Op2
- .text:00000A68 MOVS R7, R0 ; Rd = Op2
- .text:00000A6A BLX strlen ; Branch with Link and Exchange (immediate address)
- .text:00000A6E MOVS R1, #0 ; Rd = Op2
- .text:00000A70 MOVS R6, R0 ; Rd = Op2
- .text:00000A72 MOV R8, R1 ; Rd = Op2
- .text:00000A74 CMP R0, #0 ; Set cond. codes on Op1 - Op2
- .text:00000A76 BGT loc_A80 ; Branch
- .text:00000A78 B loc_AF6 ; Branch
- .text:00000A7A ; ---------------------------------------------------------------------------
- .text:00000A7A
- .text:00000A7A loc_A7A ; CODE XREF: decode+34j
- .text:00000A7A SUBS R6, #1 ; Rd = Op1 - Op2
- .text:00000A7C CMP R6, #0 ; Set cond. codes on Op1 - Op2
- .text:00000A7E BEQ loc_B0A ; Branch
- .text:00000A80
- .text:00000A80 loc_A80 ; CODE XREF: decode+1Ej
- .text:00000A80 ADDS R3, R7, R6 ; Rd = Op1 + Op2
- .text:00000A82 SUBS R3, #1 ; Rd = Op1 - Op2
- .text:00000A84 LDRB R0, [R3] ; Load from Memory
- .text:00000A86 BL ignore ; Branch with Link
- .text:00000A8A CMP R0, #0 ; Set cond. codes on Op1 - Op2
- .text:00000A8C BNE loc_A7A ; Branch
- .text:00000A8E CMP R6, #0 ; Set cond. codes on Op1 - Op2
- .text:00000A90 BLE loc_B10 ; Branch
- .text:00000A92 LDR R2, =(unk_9024 - 0xA9E) ; Load from Memory
- .text:00000A94 MOVS R1, #0 ; Rd = Op2
- .text:00000A96 MOV R8, R1 ; Rd = Op2
- .text:00000A98 MOV R10, R2 ; Rd = Op2
- .text:00000A9A ADD R10, PC ; unk_9024 ; Rd = Op1 + Op2
- .text:00000A9C MOV R1, R10 ; Rd = Op2
- .text:00000A9E MOVS R4, #0 ; Rd = Op2
- .text:00000AA0 STR R1, [SP,#0x30+var_2C] ; Store to Memory
- .text:00000AA2
- .text:00000AA2 loc_AA2 ; CODE XREF: decode+9Cj
- .text:00000AA2 ADDS R5, R7, R4 ; Rd = Op1 + Op2
- .text:00000AA4
- .text:00000AA4 loc_AA4 ; CODE XREF: decode+5Cj
- .text:00000AA4 LDRB R0, [R5] ; Load from Memory
- .text:00000AA6 BL ignore ; Branch with Link
- .text:00000AAA CMP R0, #0 ; Set cond. codes on Op1 - Op2
- .text:00000AAC BEQ loc_AB8 ; Branch
- .text:00000AAE ADDS R4, #1 ; Rd = Op1 + Op2
- .text:00000AB0 ADDS R5, #1 ; Rd = Op1 + Op2
- .text:00000AB2 CMP R4, R6 ; Set cond. codes on Op1 - Op2
- .text:00000AB4 BLT loc_AA4 ; Branch
- .text:00000AB6 ADDS R5, R7, R4 ; Rd = Op1 + Op2
- .text:00000AB8
- .text:00000AB8 loc_AB8 ; CODE XREF: decode+54j
- .text:00000AB8 LDRB R3, [R5] ; Load from Memory
- .text:00000ABA MOV R1, R10 ; Rd = Op2
- .text:00000ABC ADDS R4, #1 ; Rd = Op1 + Op2
- .text:00000ABE LDRB R3, [R1,R3] ; Load from Memory
- .text:00000AC0 MOV R9, R3 ; Rd = Op2
- .text:00000AC2 CMP R4, R6 ; Set cond. codes on Op1 - Op2
- .text:00000AC4 BLT loc_ACE ; Branch
- .text:00000AC6 B loc_B06 ; Branch
- .text:00000AC8 ; ---------------------------------------------------------------------------
- .text:00000AC8
- .text:00000AC8 loc_AC8 ; CODE XREF: decode+80j
- .text:00000AC8 ADDS R4, #1 ; Rd = Op1 + Op2
- .text:00000ACA CMP R4, R6 ; Set cond. codes on Op1 - Op2
- .text:00000ACC BEQ loc_B06 ; Branch
- .text:00000ACE
- .text:00000ACE loc_ACE ; CODE XREF: decode+6Cj
- .text:00000ACE LDRB R0, [R7,R4] ; Load from Memory
- .text:00000AD0 ADDS R5, R7, R4 ; Rd = Op1 + Op2
- .text:00000AD2 BL ignore ; Branch with Link
- .text:00000AD6 CMP R0, #0 ; Set cond. codes on Op1 - Op2
- .text:00000AD8 BNE loc_AC8 ; Branch
- .text:00000ADA
- .text:00000ADA loc_ADA ; CODE XREF: decode+B0j
- .text:00000ADA MOV R1, R9 ; Rd = Op2
- .text:00000ADC LDRB R2, [R5] ; Load from Memory
- .text:00000ADE LSLS R3, R1, #4 ; Logical Shift Left
- .text:00000AE0 LDR R1, [SP,#0x30+var_2C] ; Load from Memory
- .text:00000AE2 ADDS R4, #1 ; Rd = Op1 + Op2
- .text:00000AE4 LDRB R2, [R1,R2] ; Load from Memory
- .text:00000AE6 ORRS R3, R2 ; Rd = Op1 | Op2
- .text:00000AE8 MOV R2, R11 ; Rd = Op2
- .text:00000AEA ADD R2, R8 ; Rd = Op1 + Op2
- .text:00000AEC STRB R3, [R2] ; Store to Memory
- .text:00000AEE MOVS R3, #1 ; Rd = Op2
- .text:00000AF0 ADD R8, R3 ; Rd = Op1 + Op2
- .text:00000AF2 CMP R4, R6 ; Set cond. codes on Op1 - Op2
- .text:00000AF4 BLT loc_AA2 ; Branch
- .text:00000AF6
- .text:00000AF6 loc_AF6 ; CODE XREF: decode+20j
- .text:00000AF6 ; decode+B6j ...
- .text:00000AF6 ADD SP, SP, #0xC ; Rd = Op1 + Op2
- .text:00000AF8 MOV R0, R8 ; Rd = Op2
- .text:00000AFA POP {R2-R5} ; Pop registers
- .text:00000AFC MOV R8, R2 ; Rd = Op2
- .text:00000AFE MOV R9, R3 ; Rd = Op2
- .text:00000B00 MOV R10, R4 ; Rd = Op2
- .text:00000B02 MOV R11, R5 ; Rd = Op2
- .text:00000B04 POP {R4-R7,PC} ; Pop registers
- .text:00000B06 ; ---------------------------------------------------------------------------
- .text:00000B06
- .text:00000B06 loc_B06 ; CODE XREF: decode+6Ej
- .text:00000B06 ; decode+74j
- .text:00000B06 ADDS R5, R7, R4 ; Rd = Op1 + Op2
- .text:00000B08 B loc_ADA ; Branch
- .text:00000B0A ; ---------------------------------------------------------------------------
- .text:00000B0A
- .text:00000B0A loc_B0A ; CODE XREF: decode+26j
- .text:00000B0A MOVS R3, #0 ; Rd = Op2
- .text:00000B0C MOV R8, R3 ; Rd = Op2
- .text:00000B0E B loc_AF6 ; Branch
- .text:00000B10 ; ---------------------------------------------------------------------------
- .text:00000B10
- .text:00000B10 loc_B10 ; CODE XREF: decode+38j
- .text:00000B10 MOVS R2, #0 ; Rd = Op2
- .text:00000B12 MOV R8, R2 ; Rd = Op2
- .text:00000B14 B loc_AF6 ; Branch
- .text:00000B14 ; End of function decode
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