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- //*******************************************************************************
- // MSP-FET430P140 Demo - Timer_A, PWM TA1-2, Up Mode, DCO SMCLK
- //
- // Description: This program generates two PWM outputs on P1.2,3 using
- // Timer_A configured for up mode. The value in CCR0, 512-1, defines the PWM
- // period and the values in CCR1 and CCR2 the PWM duty cycles. Using ~800kHz
- // SMCLK as TACLK, the timer period is ~640us with a 75% duty cycle on P1.2
- // and 25% on P1.3.
- // ACLK = n/a, SMCLK = MCLK = TACLK = default DCO ~800kHz.
- //
- // MSP430F149
- // -----------------
- // /|\| XIN|-
- // | | |
- // --|RST XOUT|-
- // | |
- // | P1.2/TA1|--> CCR1 - 75% PWM
- // | P1.3/TA2|--> CCR2 - 25% PWM
- //
- // M. Buccini
- // Texas Instruments Inc.
- // Feb 2005
- // Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
- //******************************************************************************
- #include
- void main(void)
- {
- WDTCTL = WDTPW + WDTHOLD; // Stop WDT
- P1DIR |= 0x0C; // P1.2 and P1.3 output
- P1SEL |= 0x0C; // P1.2 and P1.3 TA1/2 otions
- CCR0 = 512-1; // PWM Period
- CCTL1 = OUTMOD_7; // CCR1 reset/set
- CCR1 = 384; // CCR1 PWM duty cycle
- CCTL2 = OUTMOD_7; // CCR2 reset/set
- CCR2 = 128; // CCR2 PWM duty cycle
- TACTL = TASSEL_2 + MC_1; // SMCLK, up mode
- _BIS_SR(LPM0_bits); // Enter LPM0
- }
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