15.4.13 IFG2, Interrupt Flag Register 2 ..............中断标志寄存器 .............. 444
15.4.14 UC1IE, USCI_A1 Interrupt Enable Register ..........中断使能 ............. 445
15.4.15 UC1IFG, USCI_A1 Interrupt Flag Register ............中断标志 ............ 445
16
Universal Serial Communication Interface, SPI Mode
通用串行通讯接口，SPI模式 .................................. 447
16.1
USCI Overview ......................................................... 448
16.2
USCI Introduction: SPI Mode ......................................... 448
16.3
USCI Operation: SPI Mode ........................................... 450
16.3.1 USCI Initialization and Reset ............................... 450
16.3.2 Character Format ............................................ 451
16.3.3 Master Mode ............................. .主模式. ..... 451
16.3.4 Slave Mode .................................从属模式. ...... 452
16.3.5 SPI Enable ..................................接口使 .................. 453
16.3.6 Serial Clock Control .........................串行时钟控制 .... 453
16.3.7 Using the SPI Mode With Low-Power Modes .低功耗方式 使用SPI模式. ...... 454
16.3.8 SPI Interrupts ..................................中断 ....... 454
16.4
USCI Registers: SPI Mode ........................................... 456
16.4.1 UCAxCTL0, USCI_Ax Control Register 0, UCBxCTL0, USCI_Bx Control Register 0 .控制 . 457
16.4.2 UCAxCTL1, USCI_Ax Control Register 1, UCBxCTL1, USCI_Bx Control Register 1 ................ 457
16.4.3 UCAxBR0, USCI_Ax Bit Rate Control Register 0, UCBxBR0, USCI_Bx Bit Rate Control Register
0 ...................................码率控制寄 ....... 458
16.4.4 UCAxBR1, USCI_Ax Bit Rate Control Register 1, UCBxBR1, USCI_Bx Bit Rate Control Register
1 ................................................................. 458
16.4.5 UCAxSTAT, USCI_Ax Status Register, UCBxSTAT, USCI_Bx Status Register ...状态寄 458
16.4.6 UCAxRXBUF, USCI_Ax Receive Buffer Register, UCBxRXBUF, USCI_Bx Receive Buffer
Register ..............................接收缓冲区 .. 458
16.4.7 UCAxTXBUF, USCI_Ax Transmit Buffer Register, UCBxTXBUF, USCI_Bx Transmit Buffer
Register ........................................................ 459
16.4.8 IE2, Interrupt Enable Register 2 .............................中断使能寄 ..... 459
16.4.9 IFG2, Interrupt Flag Register 2 ........................... ..中断标志寄 459
16.4.10 UC1IE, USCI_A1/USCI_B1 Interrupt Enable Register ......................... 460
16.4.11 UC1IFG, USCI_A1/USCI_B1 Interrupt Flag Register .......................... 460
17
Universal Serial Communication Interface, I 2 C Mode ................................... 461
17.1
USCI Overview ......................................................... 462
17.2
USCI Introduction: I 2 C Mode ......................................... 462
17.3
USCI Operation: I 2 C Mode ............................................ 463
17.3.1 USCI Initialization and Reset ............................... 464
17.3.2 I 2 C Serial Data ............................串行数据 ..... 464
17.3.3 I 2 C Addressing Modes ....................寻址模式 ..... 465
17.3.4 I 2 C Module Operating Modes ............操作模式. .... 466
17.3.5 I 2 C Clock Generation and Synchronization ...时钟和同步 ！！！！！........ 476
17.3.6 Using the USCI Module in I 2 C Mode with Low-Power Modes .................. 477
17.3.7 USCI Interrupts in I 2 C Mode ................................ 477
17.4
USCI Registers: I 2 C Mode ............................................ 479
17.4.1 UCBxCTL0, USCI_Bx Control Register 0 ......................................... 480
17.4.2 UCBxCTL1, USCI_Bx Control Register 1 ......................................... 481
17.4.3 UCBxBR0, USCI_Bx Baud Rate Control Register 0 ............................. 481
17.4.4 UCBxBR1, USCI_Bx Baud Rate Control Register 1 ............................. 481
17.4.5 UCBxSTAT, USCI_Bx Status Register ............................................ 482
17.4.6 UCBxRXBUF, USCI_Bx Receive Buffer Register ................................ 482
17.4.7 UCBxTXBUF, USCI_Bx Transmit Buffer Register ................................ 482
17.4.8 UCBxI2COA, USCIBx I 2 C Own Address Register ................................ 483
17.4.9 UCBxI2CSA, USCI_Bx I 2 C Slave Address Register ............................. 483
17.4.10 UCBxI2CIE, USCI_Bx I 2 C Interrupt Enable Register ........................... 483
17.4.11 IE2, Interrupt Enable Register 2 ................................................... 484
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