学习Hercules 从_c_int00了解Hercules的初始化过程！

蓝雨夜 · 2012-11-19 23:30 上传

学习Hercules 从_c_int00了解Hercules的初始化过程！ [复制链接]

在IAR工程项目配置中
Linker/Library/Override default program entry
Entery symbol 中填入 _c_int00

在download and debug 后就直接跳到右边 _c_int00 函数

该函数与 “Initialization of the TMS570LS043x, TMS570LS033x and RM42L432 Hercules ARM Cortex-R4 Microcontrollers.pdf”文件结合起来可以了解Hercules初始化中到底做了重要工作！

蓝雨夜 · 发表于2012-11-20 13:45

2. Enable the Flash interface module's response to an ECC error indicated by the CPU on accesses to Flash
      启用闪存接口模块的响应表示CPU访问到Flash的ECC错误

函数：_coreEnableFlashEcc_
文件：sys_core.asm

在初始化文件中并没有找到调用这个函数
解释参考：为了有效地使用的ECC功能，所有这些功能都相关的ECC和每个特征将需要用各自的函数调用启动。默认情况下，它们都将被禁用
http://e2e.ti.com/support/microc ... f/312/t/141752.aspx

;-------------------------------------------------------------------------------
; Enable Flash ECC Support

public    _coreEnableFlashEcc_

_coreEnableFlashEcc_

      stmfd sp!, {r0}
      mrc p15, #0x00, r0,       c1, c0,  #0x01
      orr r0,  r0, #0x02000000
      dmb
      mcr p15, #0x00, r0,       c1, c0,  #0x01
      ldmfd sp!, {r0}
      bx lr

[ 本帖最后由蓝雨夜于 2012-11-20 13:48 编辑 ]

蓝雨夜 · 2012-11-20 07:21 上传

Initialization of Hercules™ ARM® Cortex™-R4F Microcontrollers.pdf
[url=https://bbs.eeworld.com.cn/forum-154-1.html][/url]

tiankai001 · 发表于2012-11-20 08:33

感谢分享，学习一下

蓝雨夜 · 发表于2012-11-20 13:00

1. Initialize the CPU registers, including stack pointers
函数：_coreInitRegisters_();
文件：sys_core.asm

初始化的Cortex™-R4寄存器
TMS570LS043x, TMS570LS033x, and RM42L432系列微控制器包括双核Cortex-R4处理器运行在锁步（lock-step）的操作模式。
一个核心比较模块（CCM-R 4）的输出信号来自每个R4的CPU进行比较。
在两个CPU的任何差别，输出是一个高危险性级别的故障标记。
CPU内部寄存器都不能保证在上电时，两个 CPU在相同的状态下。
在函数调用，CPU推压内部寄存器到堆寨中，这可能导致内核检测比较错误。
因此，CPU内部核心寄存器必须在任何函数调用的状态前被一个预定义的初始化。
CPU的调用返回堆栈由4进入循环缓冲区。
当CPU预取单元（PFU）检测所拍摄的过程调用指令，PFU将返回地址到调用返回堆栈。
PFU认识过程调用的指令，在两个ARM®和Thumb指令

;-------------------------------------------------------------------------------
; Initialize CPU Registers

public    _coreInitRegisters_

_coreInitRegisters_

; After reset, the CPU is in the Supervisor mode (M = 10011)
      mov r0, lr
      mov r1, #0x0000
      mov r2, #0x0000
      mov r3, #0x0000
      mov r4, #0x0000
      mov r5, #0x0000
      mov r6, #0x0000
      mov r7, #0x0000
      mov r8, #0x0000
      mov r9, #0x0000
      mov r10, #0x0000
      mov r11, #0x0000
      mov r12, #0x0000
      mov r13, #0x0000
      mrs r1, cpsr
      msr spsr_cxsf, r1
      ; Switch to FIQ mode (M = 10001)
      cps #17
      mov lr, r0
      mov r8, #0x0000
      mov r9, #0x0000
      mov r10, #0x0000
      mov r11, #0x0000
      mov r12, #0x0000
      mrs r1, cpsr
      msr spsr_cxsf, r1
      ; Switch to IRQ mode (M = 10010)
      cps #18
      mov lr, r0
      mrs r1,cpsr
      msr spsr_cxsf, r1
      ; Switch to Abort mode (M = 10111)
      cps #23
      mov lr, r0
      mrs r1,cpsr
      msr spsr_cxsf, r1
      ; Switch to Undefined Instruction Mode (M = 11011)
      cps #27
      mov lr, r0
      mrs r1,cpsr
      msr spsr_cxsf, r1
      ; Switch back to Supervisor Mode (M = 10011)
      cps #19

      mrc p15,    #0x00,    r2,    c1, c0, #0x02
      orr r2,    r2,       #0xF00000
      mcr p15,    #0x00,    r2,    c1, c0, #0x02
      mov r2,    #0x40000000
      fmxr  fpexc, r2

fmdrr d0,       r1,    r1
      fmdrr d1,       r1,    r1
      fmdrr d2,       r1,    r1
      fmdrr d3,       r1,    r1
      fmdrr d4,       r1,    r1
      fmdrr d5,       r1,    r1
      fmdrr d6,       r1,    r1
      fmdrr d7,       r1,    r1
      fmdrr d8,       r1,    r1
      fmdrr d9,       r1,    r1
      fmdrr d10,       r1,    r1
      fmdrr d11,       r1,    r1
      fmdrr d12,       r1,    r1
      fmdrr d13,       r1,    r1
      fmdrr d14,       r1,    r1
      fmdrr d15,       r1,    r1
      bl next1
next1
      bl next2
next2
      bl next3
next3
      bl next4
next4
      bx r0

[ 本帖最后由蓝雨夜于 2012-11-20 13:49 编辑 ]

蓝雨夜 · 发表于2012-11-20 13:03

清除不同工作模式下的寄存器值
超级用户模式
FIQ模式
IRQ模式
中止模式
未定义指令模式
管理模式

然后初始化堆栈指针

函数：_coreInitStackPointer_();
文件：sys_core.asm

;-------------------------------------------------------------------------------
; Initialize Stack Pointers

public    _coreInitStackPointer_

_coreInitStackPointer_

      cps #17
      ldr sp,    fiqSp
      cps #18
      ldr sp,    irqSp
      cps #23
      ldr sp,    abortSp
      cps #27
      ldr sp,    undefSp
      cps #31
      ldr sp,    userSp
      cps #19
      ldr sp,    svcSp
      bx lr

[ 本帖最后由蓝雨夜于 2012-11-20 13:51 编辑 ]

蓝雨夜 · 发表于2012-11-20 13:47

3. Enable the CPU's Event Bus export mechanism
函数：_coreEnableEventBusExport_();
文件：sys_core.asm

;-------------------------------------------------------------------------------
; Enable Event Bus Export

public    _coreEnableEventBusExport_

_coreEnableEventBusExport_

      stmfd sp!, {r0}
      mrc p15, #0x00, r0,       c9, c12, #0x00
      orr r0,  r0, #0x10
      mcr p15, #0x00, r0,       c9, c12, #0x00
      ldmfd sp!, {r0}
      bx lr

蓝雨夜 · 发表于2012-11-21 13:36

4.复位处理程序：下面的指令系统异常状态寄存器读取识别CPU复位的原因。
PDF中：5. Handle the cause of reset to determine whether or not to continue with the start-up sequence

      /*检查电源上电复位条件*/
      if ((SYS_EXCEPTION & POWERON_RESET) != 0)
      {
            /*清除所有的复位状态标志*/
            SYS_EXCEPTION = 0xFFFF;

      _errata_CORTEXR4_66_();

      _errata_CORTEXR4_57_();

            /* 继续正常启动序列 */
      }/*振荡器故障*/
      else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0)
      {
            /* 振荡器故障引起的复位，在这里添加振荡器故障处理用户代码*/
      }
      else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0 )
      {
            /* 检查看门狗状态寄存器 */
         if(WATCHDOG_STATUS != 0U)
            {
                  /* 在这里添加用户的代码，处理看门狗冲突。*/

                  /*清除看门狗复位标志在异常状态寄存器 */
                  SYS_EXCEPTION = WATCHDOG_RESET;
            }
            else
            {
                  /*清除异常状态的的ICEPICK复位标志寄存器 */
                  SYS_EXCEPTION = ICEPICK_RESET;
            }
      }
      else if ((SYS_EXCEPTION & CPU_RESET) !=0 )
      {
            /* /复位引起CPU复位.
            CPU复位，可引起CPU自检完成, 通过切换“CPU复位”位CPU复位控制寄存器 */

            /* 清除所有复位状态标志 */
            SYS_EXCEPTION = CPU_RESET;
      }
      else if ((SYS_EXCEPTION & SW_RESET) != 0)
      {
            / *软件复位引起的复位。添加用户的代码来处理软件复位。 * /
      }
      else
      {
            /*由NRST被外部拉低造成的复位。添加用户代码来处理外部复位。 * /
      }

[ 本帖最后由蓝雨夜于 2012-11-21 16:17 编辑 ]

蓝雨夜 · 发表于2012-11-21 16:32

5、若上电期间  检查指出任何ESM组3错误
它是不安全的继续执行和微控制器的初始化过程可以停止在这一点上，假设没有任何ESM组3上电期间的错误  可以在这个序列中接下来的步骤
6、Check if any ESM group3 error was indicated during power-up. If any ESM group3 error occurred
during the power-up, it is not safe to continue code execution and the microcontroller initialization
process can be stopped at this point. The subsequent steps in this sequence assume that there was
no ESM group3 error during power-up.

if (esmREG->ESTATUS1[2])
{
      while(1);

}

*实验过程中，直接进入while(1); 我直接注释掉，先看下面运行情况*

蓝雨夜 · 发表于2012-11-21 16:46

6、系统初始化
函数：systemInit();
文件：system.c
PDF:
6、 Initialize System - Clock, Flash settings with Efuse self check
7. Configure phase-locked loop (PLL) control registers with the largest value for the last-stage of the dividers (R-dividers)
8. Enable the PLLs
9. Run the eFuse controller start-up checks and start the self-test on the eFuse controller SECDED logic
10. Release the peripherals from reset and enable clocks to all peripherals
11. Set up the device-level multiplexing options as well as the input/output (I/O) multiplexing.
12. Wait for the eFuse controller ECC logic self-test to complete and check the results.
13. Set up the Flash module for the required wait states and pipelined mode
14. Set up the Flash bank and pump power modes
15. Trim the LPO
16. Run the self-test on the SECDED logic embedded inside the Flash module
17. Wait for main PLL output to become valid.
18. Map the device clock domains to the desired clock sources
19. Reduce the values of the R-dividers in steps to attain the target PLL output frequency for both PLL1 and PLL2.

void systemInit(void)
{

/* Configure PLL control registers and enable PLLs.
  * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock.
  * This initialization sequence performs all the tasks that are not
  * required to be done at full application speed while the PLL locks.
  */
setupPLL();

/* Run eFuse controller start-up checks and start eFuse controller ECC self-test.
  * This includes a check for the eFuse controller error outputs to be stuck-at-zero.
  */
efcCheck();

/* Enable clocks to peripherals and release peripheral reset */
periphInit();

/* Configure device-level multiplexing and I/O multiplexing */
muxInit();

/* Wait for eFuse controller self-test to complete and check results */
if (!checkefcSelfTest())    /* eFuse controller ECC logic self-test failed */
{
  efcClass2Error();       /* device operation is not reliable */
}

/** - Set up flash address and data wait states based on the target CPU clock frequency
  * The number of address and data wait states for the target CPU clock frequency are specified
  * in the specific part's datasheet.
  */
setupFlash();

/** - Configure the LPO such that HF LPO is as close to 10MHz as possible */
trimLPO();
/** - Wait for PLLs to start up and map clock domains to desired clock sources */
mapClocks();

/** - set ECLK pins functional mode */
systemREG1->SYSPC1 = 0U;
/** - set ECLK pins default output value */
systemREG1->SYSPC4 = 0U;
/** - set ECLK pins output direction */
systemREG1->SYSPC2 = 1U;
/** - set ECLK pins open drain enable */
systemREG1->SYSPC7 = 0U;
/** - set ECLK pins pullup/pulldown enable */
systemREG1->SYSPC8 = 0U;
/** - set ECLK pins pullup/pulldown select */
systemREG1->SYSPC9 = 1U;
/** - Setup ECLK */
systemREG1->ECPCNTL = (0U << 24U)
                     | (0U << 23U)
                     | ((8U - 1U) & 0xFFFFU);

}

蓝雨夜 · 发表于2012-11-22 10:59

7、 PBIST自检
函数：pbistSelfCheck()
文件：sys_selftest.c
PDF:
20. Run a diagnostic check on the CPU self-test controller . A CPU reset is asserted upon
completion of the CPU self-test. Therefore, the initialization steps leading up to the reset handler willbe repeated.
21. Run the built-in self-test for the CPU (LBIST) . A CPU reset is asserted upon completion
of the CPU self-test. Therefore, the initialization steps leading up to the reset handler will be repeated.
22. Run a diagnostic check on the CPU compare module (CCM-R4) .
23. Run a diagnostic check on the memory self-test controller .
24. Start a self-test on the CPU RAM using the programmable built-in self-test (PBIST) controller and wait for this self-test to complete and pass .

pbistSelfCheck();

/* Run PBIST on CPU RAM.
  * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
  * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
  * device datasheet.
  */
pbistRun(0x08300020, /* ESRAM Single Port PBIST */
         PBIST_March13N_SP);

/* Wait for PBIST for CPU RAM to be completed */
while(!pbistIsTestCompleted());

/* Check if CPU RAM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
  /* CPU RAM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
  if(pbistPortTestStatus(PBIST_PORT0) != TRUE)
  {
         memoryPort0TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA0, pbistREG->FSRDL0);
  }
      else if(pbistPortTestStatus(PBIST_PORT1) != TRUE)
  {
         memoryPort1TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA1, pbistREG->FSRDL1);
  }
  else
  {
  /* while(1) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
   while(1);

  }
}

/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();

[ 本帖最后由蓝雨夜于 2012-11-22 11:00 编辑 ]

蓝雨夜 · 发表于2012-11-22 11:05

8、初始化CPU RAM
函数：_memoryInit_(0x1);
文件：sys_selftest.c
PDF:
25. Initialize the CPU RAM using the system module hardware initialization mechanism so that the ECC region for the CPU RAM is also initialized .

/* Initialize CPU RAM.
  * This function uses the system module's hardware for auto-initialization of memories and their
  * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
  * Hence the value 0x1 passed to the function.
  * This function will initialize the entire CPU RAM and the corresponding ECC locations.
  */

void _memoryInit_(uint32_t ram)
{

/* Enable Memory Hardware Initialization */
systemREG1->MINITGCR = 0xA;

/* Enable Memory Hardware Initialization for selected RAM's */
systemREG1->MSINENA  = ram;

/* Wait until Memory Hardware Initialization complete */
while( systemREG1->MSTCGSTAT & 0x00000100 != 0x00000100);

/* Disable Memory Hardware Initialization */
systemREG1->MINITGCR = 0x5;

}

蓝雨夜 · 发表于2012-11-22 11:10

9、启用TCRAM访问ECC检测
函数：_coreEnableRamEcc_()
文件：sys_core.asm
PDF:
26. Enable the CPU's SECDED logic for accesses to CPU RAM memory (CPU's B0TCM and B1TCM interfaces)

;-------------------------------------------------------------------------------
; Enable RAM ECC Support
public    _coreEnableRamEcc_

_coreEnableRamEcc_
      stmfd sp!, {r0}
      mrc p15, #0x00, r0,       c1, c0,  #0x01
      orr r0,  r0, #0x0C000000
      mcr p15, #0x00, r0,       c1, c0,  #0x01
      ldmfd sp!, {r0}
      bx lr

蓝雨夜 · 发表于2012-11-22 11:21

10、 开始PBIST在双端口存储器上自检
函数：void pbistRun(uint32_t raminfoL, uint32_t algomask)
文件：sys_selftest.c
PDF:
27. Start a self-test on all on-chip dual-port SRAMs using the PBIST controller

pbistRun(  0x00000000
         | 0x00000000
         | 0x00000800
         | 0x00000200
         | 0x00000040
         | 0x00000080
         | 0x00000100
         | 0x00000004
         | 0x00000008
         | 0x00000010
         | 0x00000400
         | 0x00020000
         | 0x00001000
         | 0x00040000
         | 0x00002000
         | 0x00080000
         | 0x00004000
| 0x00000000
| 0x00008000
, PBIST_March13N_DP);

函数原形
****************************************************************************************************************
void pbistRun(uint32_t raminfoL, uint32_t algomask)
{
volatile uint32_t i = 0;

/* PBIST ROM clock frequency = HCLK frequency /2 */
systemREG1->MSTGCR |= 0x00000100;

/* Enable PBIST controller */
systemREG1->MSINENA = 0x1;

/* clear MSTGENA field */
systemREG1->MSTGCR &= ~(0xF);

/* Enable PBIST self-test */
systemREG1->MSTGCR |= 0xA;

/* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
for (i=0; i<(32 + (32 * 0U)); i++);

/* Enable PBIST clocks and ROM clock */
pbistREG->PACT = 0x3;

/* Select all algorithms to be tested */
pbistREG->ALGO = algomask;

/* Select RAM groups */
pbistREG->RINFOL = raminfoL;

/* Select all RAM groups */
pbistREG->RINFOU = 0x00000000;

/* ROM contents will not override RINFOx settings */
pbistREG->OVER = 0x0;

/* Algorithm code is loaded from ROM */
pbistREG->ROM = 0x3;

/* Start PBIST */
pbistREG->DLR = 0x14;

}
****************************************************************************************************************

蓝雨夜 · 发表于2012-11-27 10:19

11、运行CPU的SECDED的逻辑访问主数据RAM的自检
文件：sys_selftest.c
函数： checkB0RAMECC();

PDF:
//检查TCRAM1的ECC错误检测逻辑
  checkB0RAMECC();
tcram1REG->RAMCTRL &= ~(0x00000100); /* disable writes to ECC RAM */
tcram2REG->RAMCTRL &= ~(0x00000100);
//检查TCRAM2的ECC错误检测逻辑
checkB1RAMECC();
tcram1REG->RAMCTRL &= ~(0x00000100); /* disable writes to ECC RAM */
tcram2REG->RAMCTRL &= ~(0x00000100);

/* 等待CPU RAM 的PBIST 完成 */
while(!pbistIsTestCompleted());

/* 检查CPU RAM通过自我测试*/
if( pbistIsTestPassed() != TRUE)
{

      /* CPU RAM自检失败。需要自定义处理程序检查内存故障并采取适当的下一步.*/
  if(pbistPortTestStatus(PBIST_PORT0) != TRUE)
  {
         memoryPort0TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA0, pbistREG->FSRDL0);
  }
      else if(pbistPortTestStatus(PBIST_PORT1) != TRUE)
  {
         memoryPort1TestFailNotification(pbistREG->RGS, pbistREG->RDS, pbistREG->FSRA1, pbistREG->FSRDL1);
  }
  else
  {
  /* while(1) can be removed by adding "# if 0" and "# endif" in the user codes above and below */

   while(1);
  }
}

/* 禁用PBIST时钟和禁用内存自检模式 */
pbistStop();

蓝雨夜 · 发表于2012-11-27 10:35

12、检查所有的外设存储器奇偶校验错误检测机制

文件：sys_startup.c
文件：sys_selftest.c
PDF:
35. Check the parity error detection mechanism for all peripheral memories

/* 复位释放MibSPI1模块
  * 这将导致MibSPI1 RAM获得奇偶校验存储初始化  */
  mibspiREG1->GCR0 = 0x1;

/* 复位释放MibSPI3模块
  * 这将导致MibSPI3 RAM获得奇偶校验存储初始化  */
  */
mibspiREG3->GCR0 = 0x1;

/* 复位释放MibSPI5模块
  * 这将导致MibSPI5 RAM获得奇偶校验存储初始化  */
mibspiREG5->GCR0 = 0x1;

/* 初始化所有片上SRAM的除MibSPIx RAM外
   * The MibSPIx modules have their own auto-initialization mechanism which is triggered
   * as soon as the modules are brought out of local reset.
   */
/* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
  */
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
      Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
  */
_memoryInit_(  1 << 1
               | 1 << 2
               | 1 << 5
               | 1 << 6
               | 1 << 10
               | 1 << 8
               | 1 << 14
               | 1 << 3
               | 1 << 4
               | 1 << 15
               | 1 << 16
               | 0 << 13);
/* Test the parity protection mechanism for peripheral RAMs
NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
         Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/

het1ParityCheck();

htu1ParityCheck();

het2ParityCheck();

htu2ParityCheck();

adc1ParityCheck();

adc2ParityCheck();

  can1ParityCheck();

can2ParityCheck();

can3ParityCheck();

vimParityCheck();

dmaParityCheck();

  while (mibspiREG1->BUFINIT);  /* wait for MibSPI1 RAM to complete initialization */
while (mibspiREG3->BUFINIT);  /* wait for MibSPI3 RAM to complete initialization */
while (mibspiREG5->BUFINIT);  /* wait for MibSPI5 RAM to complete initialization */

mibspi1ParityCheck();

  mibspi3ParityCheck();

mibspi5ParityCheck();

蓝雨夜 · 发表于2012-11-27 10:41

13、使能 IRQ 偏移量 Vic 控制器 */

文件：sys_startup.c
函数：_coreEnableIrqVicOffset_();

PDF:
36. Enable the CPU’s dedicated vectored interrupt controller (VIC) port
37. Program all interrupt service routine addresses in the vectored interrupt manager (VIM) memory
38. Configure IRQ and FIQ interrupt priorities for all interrupt channels
39. Enable the desired interrupts (IRQ or FIQ) inside the CPU
40. Enable the desired interrupts in the VIM control registers

/* Enable IRQ offset via Vic controller */
_coreEnableIrqVicOffset_();

/* 初始化VIM表*/
{
      uint32_t i;
      for (i = 0; i < (VIM_CHANNELS + 1); i++)
      {
         vimRAM->ISR = s_vim_init;
      }
}
/* 设置IRQ/ FIQ优先级 */
vimREG->FIRQPR0 =  SYS_FIQ
                  | (SYS_FIQ <<  1U)
                  | (SYS_IRQ <<  2U)
                  | (SYS_IRQ <<  3U)
                  | (SYS_IRQ <<  4U)
                  | (SYS_IRQ <<  5U)
                  | (SYS_IRQ <<  6U)
                  | (SYS_IRQ <<  7U)
                  | (SYS_IRQ <<  8U)
                  | (SYS_IRQ <<  9U)
                  | (SYS_IRQ << 10U)
                  | (SYS_IRQ << 11U)
                  | (SYS_IRQ << 12U)
                  | (SYS_IRQ << 13U)
                  | (SYS_IRQ << 14U)
                  | (SYS_IRQ << 15U)
                  | (SYS_IRQ << 16U)
                  | (SYS_IRQ << 17U)
                  | (SYS_IRQ << 18U)
                  | (SYS_IRQ << 19U)
                  | (SYS_IRQ << 20U)
                  | (SYS_IRQ << 21U)
                  | (SYS_IRQ << 22U)
                  | (SYS_IRQ << 23U)
                  | (SYS_IRQ << 24U)
                  | (SYS_IRQ << 25U)
                  | (SYS_IRQ << 26U)
                  | (SYS_IRQ << 27U)
                  | (SYS_IRQ << 28U)
                  | (SYS_IRQ << 29U)
                  | (SYS_IRQ << 30U)
                  | (SYS_IRQ << 31U);
vimREG->FIRQPR1 =  SYS_IRQ
                  | (SYS_IRQ <<  1U)
                  | (SYS_IRQ <<  2U)
                  | (SYS_IRQ <<  3U)
                  | (SYS_IRQ <<  4U)
                  | (SYS_IRQ <<  5U)
                  | (SYS_IRQ <<  6U)
                  | (SYS_IRQ <<  7U)
                  | (SYS_IRQ <<  8U)
                  | (SYS_IRQ <<  9U)
                  | (SYS_IRQ << 10U)
                  | (SYS_IRQ << 11U)
                  | (SYS_IRQ << 12U)
                  | (SYS_IRQ << 13U)
                  | (SYS_IRQ << 14U)
                  | (SYS_IRQ << 15U)
                  | (SYS_IRQ << 16U)
                  | (SYS_IRQ << 17U)
                  | (SYS_IRQ << 18U)
                  | (SYS_IRQ << 19U)
                  | (SYS_IRQ << 20U)
                  | (SYS_IRQ << 21U)
                  | (SYS_IRQ << 22U)
                  | (SYS_IRQ << 23U)
                  | (SYS_IRQ << 24U)
                  | (SYS_IRQ << 25U)
                  | (SYS_IRQ << 26U)
                  | (SYS_IRQ << 27U)
                  | (SYS_IRQ << 28U)
                  | (SYS_IRQ << 29U)
                  | (SYS_IRQ << 30U)
                  | (SYS_IRQ << 31U);

vimREG->FIRQPR2 =  SYS_IRQ
                  | (SYS_IRQ << 1U)
                  | (SYS_IRQ << 2U)
                  | (SYS_IRQ << 3U)
                  | (SYS_IRQ << 4U)
                  | (SYS_IRQ << 5U)
                  | (SYS_IRQ << 6U)
                  | (SYS_IRQ << 7U)
                  | (SYS_IRQ << 8U)
                  | (SYS_IRQ << 9U)
                  | (SYS_IRQ << 10U)
                  | (SYS_IRQ << 11U)
                  | (SYS_IRQ << 12U)
                  | (SYS_IRQ << 13U)
                  | (SYS_IRQ << 14U)
                  | (SYS_IRQ << 15U)
                  | (SYS_IRQ << 16U)
                  | (SYS_IRQ << 17U)
                  | (SYS_IRQ << 18U)
                  | (SYS_IRQ << 19U)
                  | (SYS_IRQ << 20U)
                  | (SYS_IRQ << 21U)
                  | (SYS_IRQ << 22U)
                  | (SYS_IRQ << 23U)
                  | (SYS_IRQ << 24U)
                  | (SYS_IRQ << 25U)
   | (SYS_IRQ << 26U)
                  | (SYS_IRQ << 27U)
                  | (SYS_IRQ << 28U)
                  | (SYS_IRQ << 29U)
                  | (SYS_IRQ << 30U)
                  | (SYS_IRQ << 31U);
vimREG->FIRQPR3 =  SYS_IRQ
                  | (SYS_IRQ << 1U)
                  | (SYS_IRQ << 2U)
                  | (SYS_IRQ << 3U)
                  | (SYS_IRQ << 4U)
                  | (SYS_IRQ << 5U)
                  | (SYS_IRQ << 6U)
                  | (SYS_IRQ << 7U)
                  | (SYS_IRQ << 8U)
                  | (SYS_IRQ << 9U)
                  | (SYS_IRQ << 10U)
                  | (SYS_IRQ << 11U)
                  | (SYS_IRQ << 12U)
                  | (SYS_IRQ << 13U)
                  | (SYS_IRQ << 14U)
                  | (SYS_IRQ << 15U)
                  | (SYS_IRQ << 16U)
                  | (SYS_IRQ << 17U)
                  | (SYS_IRQ << 18U)
                  | (SYS_IRQ << 19U)
                  | (SYS_IRQ << 20U)
                  | (SYS_IRQ << 21U)
                  | (SYS_IRQ << 22U)
                  | (SYS_IRQ << 23U)
                  | (SYS_IRQ << 24U)
                  | (SYS_IRQ << 25U)
   | (SYS_IRQ << 26U)
                  | (SYS_IRQ << 27U)
                  | (SYS_IRQ << 28U)
                  | (SYS_IRQ << 29U)
                  | (SYS_IRQ << 30U)
                  | (SYS_IRQ << 31U);

/* enable interrupts */
vimREG->REQMASKSET0 = 1U
                     | (1U << 1U)
                     | (0U << 2U)
                     | (0U << 3U)
                     | (0U << 4U)
                     | (0U << 5U)
                     | (0U << 6U)
                     | (0U << 7U)
                     | (0U << 8U)
                     | (0U << 9U)
                     | (0U << 10U)
                     | (0U << 11U)
                     | (0U << 12U)
                     | (0U << 13U)
                     | (0U << 14U)
                     | (0U << 15U)
                     | (0U << 16U)
                     | (0U << 17U)
                     | (0U << 18U)
                     | (0U << 19U)
                     | (0U << 20U)
                     | (0U << 21U)
                     | (0U << 22U)
                     | (0U << 23U)
                     | (0U << 24U)
                     | (0U << 25U)
                     | (0U << 26U)
                     | (0U << 27U)
                     | (0U << 28U)
                     | (0U << 29U)
                     | (0U << 30U)
                     | (0U << 31U);
vimREG->REQMASKSET1 = 0U
                     | (0U << 1U)
                     | (0U << 2U)
                     | (0U << 3U)
                     | (0U << 4U)
                     | (0U << 5U)
                     | (0U << 6U)
                     | (0U << 7U)
                     | (0U << 8U)
                     | (0U << 9U)
                     | (0U << 10U)
                     | (0U << 11U)
                     | (0U << 12U)
                     | (0U << 13U)
                     | (0U << 14U)
                     | (0U << 15U)
                     | (0U << 16U)
                     | (0U << 17U)
                     | (0U << 18U)
                     | (0U << 19U)
                     | (0U << 20U)
                     | (0U << 21U)
                     | (0U << 22U)
                     | (0U << 23U)
                     | (0U << 24U)
                     | (0U << 25U)
                     | (0U << 26U)
                     | (0U << 27U)
                     | (0U << 28U)
                     | (0U << 29U)
                     | (0U << 30U)
                     | (0U << 31U);
vimREG->REQMASKSET2 = 0U
                     | (0U << 1U)
                     | (0U << 2U)
                     | (0U << 3U)
                     | (0U << 4U)
                     | (0U << 5U)
                     | (0U << 6U)
                     | (0U << 7U)
                     | (0U << 8U)
                     | (0U << 9U)
                     | (0U << 10U)
                     | (0U << 11U)
                     | (0U << 12U)
                     | (0U << 13U)
                     | (0U << 14U)
                     | (0U << 15U)
                     | (0U << 16U)
                     | (0U << 17U)
                     | (0U << 18U)
                     | (0U << 19U)
                     | (0U << 20U)
                     | (0U << 21U)
                     | (0U << 22U)
                     | (0U << 23U)
                     | (0U << 24U)
                     | (0U << 25U)
      | (0U << 26U)
                     | (0U << 27U)
                     | (0U << 28U)
                     | (0U << 29U)
                     | (0U << 30U)
                     | (0U << 31U);

vimREG->REQMASKSET3 =  0U
                     | (0U << 1U)
                     | (0U << 2U)
                     | (0U << 3U)
                     | (0U << 4U)
                     | (0U << 5U)
                     | (0U << 6U)
                     | (0U << 7U)
                     | (0U << 8U)
                     | (0U << 9U)
                     | (0U << 10U)
                     | (0U << 11U)
                     | (0U << 12U)
                     | (0U << 13U)
                     | (0U << 14U)
                     | (0U << 15U)
                     | (0U << 16U)
                     | (0U << 17U)
                     | (0U << 18U)
                     | (0U << 19U)
                     | (0U << 20U)
                     | (0U << 21U)
                     | (0U << 22U)
                     | (0U << 23U)
                     | (0U << 24U)
                     | (0U << 25U)
   | (0U << 26U)
                     | (0U << 27U)
                     | (0U << 28U)
                     | (0U << 29U)
                     | (0U << 30U)
                     | (0U << 31U);

蓝雨夜 · 发表于2012-11-27 10:45

14、配置系统响应错误条件的信号到ESM组别
文件：esm.c
函数：esmInit();

PDF:
41. Set up the application responses to inputs to the error signaling module (ESM)

函数原形

void esmInit(void)
{
/* USER CODE BEGIN (3) */
/* USER CODE END */
/** - Disable error pin channels */
esmREG->EPENACLR1 = 0xFFFFFFFFU;
esmREG->EPENACLR4 = 0xFFFFFFFFU;
/** - Disable interrupts */
esmREG->INTENACLR1 = 0xFFFFFFFFU;
esmREG->INTENACLR4 = 0xFFFFFFFFU;
/** - Clear error status flags */
esmREG->ESTATUS1[0U] = 0xFFFFFFFFU;
esmREG->ESTATUS1[1U] = 0xFFFFFFFFU;
esmREG->ESTATUS2EMU  = 0xFFFFFFFFU;
esmREG->ESTATUS1[2U] = 0xFFFFFFFFU;
esmREG->ESTATUS4[0U] = 0xFFFFFFFFU;
esmREG->ESTATUS4[1U] = 0xFFFFFFFFU;
esmREG->ESTATUS5EMU  = 0xFFFFFFFFU;
esmREG->ESTATUS4[2U] = 0xFFFFFFFFU;
/** - Setup LPC preload */
esmREG->LTCPRELOAD = 16384U - 1U;
/** - Reset error pin */
if (esmREG->EPSTATUS == 0U)
{
      esmREG->KEY = 0x00000005U;
}
else
{
      esmREG->KEY = 0x00000000U;
}
/** - Clear interrupt level */
esmREG->INTLVLCLR1 = 0xFFFFFFFFU;
esmREG->INTLVLCLR4 = 0xFFFFFFFFU;
/** - Set interrupt level */
esmREG->INTLVLSET1 = (0U << 31U)
                     | (0U << 30U)
                     | (0U << 29U)
                     | (0U << 28U)
                     | (0U << 27U)
                     | (0U << 26U)
                     | (0U << 25U)
                     | (0U << 24U)
                     | (0U << 23U)
                     | (0U << 22U)
                     | (0U << 21U)
                     | (0U << 20U)
                     | (0U << 19U)
                     | (0U << 18U)
                     | (0U << 17U)
                     | (0U << 16U)
                     | (0U << 15U)
                     | (0U << 14U)
                     | (0U << 13U)
                     | (0U << 12U)
                     | (0U << 11U)
                     | (0U << 10U)
                     | (0U <<  9U)
                     | (0U <<  8U)
                     | (0U <<  7U)
                     | (0U <<  6U)
                     | (0U <<  5U)
                     | (0U <<  4U)
                     | (0U <<  3U)
                     | (0U <<  2U)
                     | (0U <<  1U)
                     | (0U);
esmREG->INTLVLSET4 = (0U << 31U)
                     | (0U << 30U)
                     | (0U << 29U)
                     | (0U << 28U)
                     | (0U << 27U)
                     | (0U << 26U)
                     | (0U << 25U)
                     | (0U << 24U)
                     | (0U << 23U)
                     | (0U << 22U)
                     | (0U << 21U)
                     | (0U << 20U)
                     | (0U << 19U)
                     | (0U << 18U)
                     | (0U << 17U)
                     | (0U << 16U)
                     | (0U << 15U)
                     | (0U << 14U)
                     | (0U << 13U)
                     | (0U << 12U)
                     | (0U << 11U)
                     | (0U << 10U)
                     | (0U <<  9U)
                     | (0U <<  8U)
                     | (0U <<  7U)
                     | (0U <<  6U)
                     | (0U <<  5U)
                     | (0U <<  4U)
                     | (0U <<  3U)
                     | (0U <<  2U)
                     | (0U <<  1U)
                     | (0U);
/** - Enable error pin channels */
esmREG->EPENASET1 = (0U << 31U)
                  | (0U << 30U)
                  | (0U << 29U)
                  | (0U << 28U)
                  | (0U << 27U)
                  | (0U << 26U)
                  | (0U << 25U)
                  | (0U << 24U)
                  | (0U << 23U)
                  | (0U << 22U)
                  | (0U << 21U)
                  | (0U << 20U)
                  | (0U << 19U)
                  | (0U << 18U)
                  | (0U << 17U)
                  | (0U << 16U)
                  | (0U << 15U)
                  | (0U << 14U)
                  | (0U << 13U)
                  | (0U << 12U)
                  | (0U << 11U)
                  | (0U << 10U)
                  | (0U <<  9U)
                  | (0U <<  8U)
                  | (0U <<  7U)
                  | (0U <<  6U)
                  | (0U <<  5U)
                  | (0U <<  4U)
                  | (0U <<  3U)
                  | (0U <<  2U)
                  | (0U <<  1U)
                  | (0U);
esmREG->EPENASET4 = (0U << 31U)
                  | (0U << 30U)
                  | (0U << 29U)
                  | (0U << 28U)
                  | (0U << 27U)
                  | (0U << 26U)
                  | (0U << 25U)
                  | (0U << 24U)
                  | (0U << 23U)
                  | (0U << 22U)
                  | (0U << 21U)
                  | (0U << 20U)
                  | (0U << 19U)
                  | (0U << 18U)
                  | (0U << 17U)
                  | (0U << 16U)
                  | (0U << 15U)
                  | (0U << 14U)
                  | (0U << 13U)
                  | (0U << 12U)
                  | (0U << 11U)
                  | (0U << 10U)
                  | (0U <<  9U)
                  | (0U <<  8U)
                  | (0U <<  7U)
                  | (0U <<  6U)
                  | (0U <<  5U)
                  | (0U <<  4U)
                  | (0U <<  3U)
                  | (0U <<  2U)
                  | (0U <<  1U)
                  | (0U);
/** - Enable interrupts */
esmREG->INTENASET1 = (0U << 31U)
                     | (0U << 30U)
                     | (0U << 29U)
                     | (0U << 28U)
                     | (0U << 27U)
                     | (0U << 26U)
                     | (0U << 25U)
                     | (0U << 24U)
                     | (0U << 23U)
                     | (0U << 22U)
                     | (0U << 21U)
                     | (0U << 20U)
                     | (0U << 19U)
                     | (0U << 18U)
                     | (0U << 17U)
                     | (0U << 16U)
                     | (0U << 15U)
                     | (0U << 14U)
                     | (0U << 13U)
                     | (0U << 12U)
                     | (0U << 11U)
                     | (0U << 10U)
                     | (0U <<  9U)
                     | (0U <<  8U)
                     | (0U <<  7U)
                     | (0U <<  6U)
                     | (0U <<  5U)
                     | (0U <<  4U)
                     | (0U <<  3U)
                     | (0U <<  2U)
                     | (0U <<  1U)
                     | (0U);
esmREG->INTENASET4 = (0U << 31U)
                     | (0U << 30U)
                     | (0U << 29U)
                     | (0U << 28U)
                     | (0U << 27U)
                     | (0U << 26U)
                     | (0U << 25U)
                     | (0U << 24U)
                     | (0U << 23U)
                     | (0U << 22U)
                     | (0U << 21U)
                     | (0U << 20U)
                     | (0U << 19U)
                     | (0U << 18U)
                     | (0U << 17U)
                     | (0U << 16U)
                     | (0U << 15U)
                     | (0U << 14U)
                     | (0U << 13U)
                     | (0U << 12U)
                     | (0U << 11U)
                     | (0U << 10U)
                     | (0U <<  9U)
                     | (0U <<  8U)
                     | (0U <<  7U)
                     | (0U <<  6U)
                     | (0U <<  5U)
                     | (0U <<  4U)
                     | (0U <<  3U)
                     | (0U <<  2U)
                     | (0U <<  1U)
                     | (0U);
/* USER CODE BEGIN (4) */
/* USER CODE END */
}

xjyprc

真是太详细了对我们菜鸟来说太有用了

siyida_01

ding and supply

学习Hercules 从_c_int00了解Hercules的初始化过程！ [复制链接]

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