quartus仿真的问题

huzi741

quartus仿真的问题 [复制链接]

Warning (10631): VHDL Process Statement warning at rams.vhd(35): inferring latch(es) for signal or variable "dout", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at Vhdl2.vhd(29): inferring latch(es) for signal or variable "dout1", which holds its previous value in one or more paths through the process
Warning: Found pins functioning as undefined clocks and/or memory enables
Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
我编辑的是一个存储矩阵，但是出现以上警告，况且仿真的时候，不能改变他的输入波形，
请各位大侠指教，

eeleader

看你WARNING可以知道：

    你CLK 不是专用管脚，导致CLK是非法路径，可能造成电路不工作，原因CLK抖动太大！

   DOUT,DOUT1输出没有变化。说明这个两个输出没有用！