ENTITY Speakera IS
PORT ( clk : IN STD_LOGIC ; --待分频时钟12M Hz
e : IN std_logic_vector(14 downto 0);--INTEGER RANGE 0 TO 16#7FF# ;--分频预置数输入
f : OUT STD_LOGIC ) ; --发声输出
END ;
--****************************************************
ARCHITECTURE one OF Speakera IS
SIGNAL q : STD_LOGIC_vector(14 downto 0) ;
SIGNAL c1,c2 : STD_LOGIC ;
BEGIN
PROCESS(clk)
BEGIN
IF e="000000000000000" THEN
c1 <= '0' ;
ELSIF clk'EVENT AND clk='1' THEN
q<=q + 1;
if q>=e then
q<="000000000000000";
c1<='1';
else
c1<='0';
END IF;
end if;
END PROCESS ;
PROCESS(c1)
BEGIN
IF c1'EVENT AND c1 = '1' THEN
c2<=not c2 ;-- 11 位可预置计数器
END IF;
END PROCESS;
f<=c2;
END one;
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