数字电压表数码管显示

博雷德

数字电压表数码管显示 [复制链接]

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-- Company:
-- Engineer:
--
-- Create Date:    10:42:01 04/22/2012
-- Design Name:
-- Module Name:    top1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top1 is
  port(
       clk   :   in   std_logic;
   ad    :   in   std_logic_vector(7 downto 0);
   an    :   OUT std_logic_vector(3 downto 0);
   a_to_h : OUT std_logic_vector(7 downto 0);
   eoc : IN std_logic;
   OE : out STD_LOGIC;
   ale : OUT std_logic;
   start : OUT std_logic;
   ADC_ONECLK: INOUT STD_LOGIC
   );
end top1;

architecture Behavioral of top1 is
signal temp  :    std_logic_vector(7 downto 0);
 COMPONENT ad_hgq
 PORT(
  d : IN std_logic_vector(7 downto 0);
  clk : IN std_logic;
  eoc : IN std_logic;   
  oneUSCLK : INOUT std_logic;     
  oe : OUT std_logic;
  ale : OUT std_logic;
  start : OUT std_logic;
  q : OUT std_logic_vector(7 downto 0)
  );
 END COMPONENT;
 COMPONENT top
 PORT(
  sw : IN std_logic_vector(7 downto 0);
  clk : IN std_logic;         
  a_to_h : OUT std_logic_vector(7 downto 0);
  an : OUT std_logic_vector(3 downto 0)
  );
 END COMPONENT;

begin
 Inst_ad_hgq: ad_hgq PORT MAP(
  d => ad,
  clk =>clk  ,
  eoc => eoc,
  oe =>oe ,
  ale =>ale ,
  start =>start ,
  q => temp,
  oneUSCLK => ADC_ONECLK
 );
 Inst_top: top PORT MAP(
  a_to_h => a_to_h,
  sw => temp ,
  clk => clk ,
  an =>an
 );

 

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ad_hgq is
  port(
        d :in std_logic_vector(7 downto 0);---AD输入；
        clk,eoc :in std_logic; ---eoc:转换结束状态信号；
        oe : out std_logic; 
        ale,start:out std_logic; ---ale:允许地址锁存；
        q :out std_logic_vector(7 downto 0);
        oneUSCLK : inout std_logic
      ); ---转换数据输出显示；       
end ad_hgq;
architecture behaviour of ad_hgq is
  type state is (st0,st1,st2,st3,st4,st5,st6,st7); ---以枚举类型定义各状态子类型；
  signal current_state,next_state :state:=st0;  
  signal regl :std_logic_vector(7 downto 0);
  signal addrx :std_logic_vector(2 downto 0):="000";
  signal lock :std_logic;          ---转换后数据输出锁存时钟信号；
  signal hex :std_logic_vector(7 downto 0);
  signal clkCount: std_logic_vector (6 downto 0);
 
  --signal oneUSCLK :std_logic;
 begin
process(current_state,eoc)
begin
 case current_state is
    when st0=> ale<='0';start<='0';oe<='0';lock<='0'; next_state<=st1;
                   ---初始态ST0向下一状态ST1转换,0809采样控制信号初始化；
    when st1=> ale<='1';start<='0';oe<='0';lock<='0'; next_state<=st2;
                   ---由ALE的上升沿将通道地址'001'锁入0809的地址寄存器；
    when st2=> ale<='1';start<='1';oe<='0';lock<='0'; next_state<=st3;  ---启动采样信号；
    when st3=> ale<='0';start<='1';oe<='0';lock<='0';
      if(eoc='0')  then  next_state<=st4; ---转换即将结束,转换至下一状态；
        else next_state<=st3;   ---转换未结束,继续在状态ST3中等待；
      end if;
    when st4=> ale<='0';start<='0';oe<='0';lock<='0';
      if(eoc='1')  then  next_state<=st5; ---EOC由0恢复1,转换结束；
        else next_state<=st4; ---转换未结束,等待；
      end if;
    when st5=> ale<='0';start<='0';oe<='1';lock<='0'; next_state<=st6;  --开启输出允许OE；
    when st6=> ale<='0';start<='0';oe<='1';lock<='1'; next_state<=st7;  --开启数据锁存LOCK；
    when st7=> ale<='0';start<='0';oe<='0';lock<='1'; next_state<=st0;
    when others=>next_state<=st0;  ---其它状态返回ST0；
 end case;
 end process;
 process (CLK)
     begin
  if (CLK = '1' and CLK'event) then
   if(clkCount = "1100011") then  --1100011--99
    clkCount <= "0000000";
    oneUSClk <= not oneUSClk;
   else
    clkCount <= clkCount + 1;
   end if;
  end if;
 end process;
process(oneUSClk)
  begin
    if(oneUSClk'event and oneUSClk='1')  then 
  current_state<=next_state;
    end if;     ---在时钟上升沿,转换至下一状态；
end process ; ---由信号current_state将当前状态带出进程,进入下一进程；
process(lock)
  begin
    if (lock='1'and lock'event)  then  regl<=d;
    end if; --在lock上升沿,将转换好的数据锁存入8位锁存器中；
end process; 
q<=regl; ---数据输出；
--process(oneUSClk)
--  begin
--    if( oneUSClk'event and oneUSClk ='1')  then  if oe='1'  then  hex<=q; ---将数据送给hex；
--  end if;
--    end if;
--end process;  
end behaviour;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity top is
       port(
        a_to_h    :    out    std_logic_vector(7 downto 0);
    sw        :    in     std_logic_vector(7 downto 0);
    clk       :    in     std_logic;
    an        :    out    std_logic_vector(3 downto 0)
    );

end top;

architecture Behavioral of top is
type mstate is
   (
    qian,
  bai,
  shi,
  ge
  );
type ConvADCState is
 (
    DispInit,
  DispConv1,
  DispConv2
 );
signal  select1  :   std_logic_vector(3 downto 0);
signal  clkcount :   std_logic_vector(6 downto 0);
signal  oneusclk  :   std_logic;
signal  regl     :   integer range 0 to 255;
signal  ADCThou,ADCHun,ADCTen,ADCNum:  integer range 0 to 9:= 0;
signal DisplayADCState : ConvADCState := DispInit;
signal weishu : mstate := qian;
signal display :integer range 0 to 9;

begin
  regl<=conv_integer(sw);
  process(clk)
  begin
    if clk='1' and clk'event  then
     if clkcount="1100011"  then
      clkcount<="0000000";
    oneusclk<= not oneusclk;
   else
      clkcount<=clkcount+1;
   end if;
  end if;
  end process;
  process(oneusclk)
  variable regl1 : integer range 0 to 49980;
  variable ADCThou1,ADCHun1,ADCTen1,ADCNum1:integer range 0 to 9;
  begin
  if (oneUSClk = '1' and oneUSClk'event) then
    case DisplayADCState is
       when DispInit=>
        regl1:=(regl)*196;
      ADCThou1:=0;
      ADCHun1:=0;
      ADCTen1:=0;
      ADCNum1:=0;
      DisplayADCState<=DispConv1;
   when DispConv1=>
        if regl1>9999 then
         ADCThou1:=ADCThou1+1;
       regl1:=regl1-10000;
       DisplayADCState<=DispConv1;
        elsif regl1>999 then
         ADCHun1:=ADCHun1+1;
       regl1:=regl1-1000;
       DisplayADCState<=DispConv1;
      elsif regl1>99 then
         ADCTen1:=ADCTen1+1;
       regl1:=regl1-100;
       DisplayADCState<=DispConv1;
      elsif regl1>9 then
         ADCNum1:=ADCNum1+1;
       regl1:=regl1-10;
       DisplayADCState<=DispConv1;
      else
         DisplayADCState<=DispConv2;
      end if;
    when DispConv2=>
        ADCThou<=ADCThou1;
        ADCHun<=ADCHun1;
      ADCTen<=ADCTen1;
      ADCNum<=ADCNum1;
      DisplayADCState <= DispInit;
     end case;
  end if;
  end process;
  process(display)
  begin
      case display is
           when 0=>a_to_h(6 downto 0)<="1000000";
           when 1=>a_to_h(6 downto 0)<="1111001";
           when 2=>a_to_h(6 downto 0)<="0100100";
           when 3=>a_to_h(6 downto 0)<="0110000";
           when 4=>a_to_h(6 downto 0)<="0011001";
           when 5=>a_to_h(6 downto 0)<="0010010";
           when 6=>a_to_h(6 downto 0)<="0000010";
           when 7=>a_to_h(6 downto 0)<="1111000";
           when 8=>a_to_h(6 downto 0)<="0000000";
           when 9=>a_to_h(6 downto 0)<="0010000";
      end case;
  end process;
  process(oneusclk,display)
  begin
  if (oneUSClk = '1' and oneUSClk'event) then
      case weishu is
       when qian=>
                an<="0111";
                display<=ADCThou;
        a_to_h(7)<='0';
        weishu<=bai;
     when bai=>
                an<="1011";
        display<=ADCHun;
        a_to_h(7)<='1';
        weishu<=shi;
     when shi=>
                an<="1101";
                display<=ADCTen;
        a_to_h(7)<='1';
        weishu<=ge;
     when ge=>
                an<="1110";
        display<=ADCNum;
        a_to_h(7)<='1';
        weishu<=qian;
   end case;
  end if;
  end process;
    
     
       
     
 
    

end Behavioral;

 

tx_xy

要是能有原理性的描述 或者方案概述 就更好啦 。。。