FPGA访问MCP3201的程序

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FPGA访问MCP3201的程序 [复制链接]

根据前面对MCP3201芯片硬件和时序研究，设计如下FPGA 程序访问MCP3201

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity get_ad_mcp3201 is
port
    (
      clk: in std_logic;    --------系统时钟20MHZ
      rst: in std_logic;    --------低电平复位
      mcp3201_ncs: out std_logic;
      mcp3201_clk: out std_logic;
      mcp3201_dout:in  std_logic;
      mcp3201_ad_data: out std_logic_vector(11 downto 0)
     );
end get_ad_mcp3201;

architecture arch_get_ad_mcp3201 of get_ad_mcp3201 is
signal state : std_logic_vector(3 downto 0);
signal clk_400k:std_logic;
signal cnt: std_logic_vector(5 downto 0);
signal data_reg: std_logic_vector(11 downto 0);
signal clk_period_num: std_logic_vector(4 downto 0);
begin
process(clk,rst)
begin
if (rst='0') then
  clk_400k<='0';
  cnt<=(others=>'0');
elsif clk'event and clk='1' then
  if (cnt="000000") then
      cnt<="110001"; ---49
      clk_400k<='1';
  else
      cnt<=cnt-"000001";
  end if;
end if;
end process;

process(clk,rst)
begin
if (rst='0') then
  mcp3201_ncs<='1';
  mcp3201_clk<='0';
  mcp3201_ad_data<=(others=>'0');
  clk_period_num<=(others=>'0');
  data_reg<=(others=>'0'); 
  state<=x"0";
elsif clk'event and clk='1' then
  if (clk_400k='1') then
       if (state=x"0") then
            mcp3201_ncs<='1';
            state<=x"1";
       elsif (state=x"1") then
            mcp3201_ncs<='0';
            mcp3201_clk<='0';
             state<=x"2";
       elsif (state=x"2") then
            mcp3201_clk<='1';
            if (clk_period_num="01110") then
                  clk_period_num<=(others=>'0');
                   state<=x"3";
            else
                  clk_period_num<=clk_period_num+"00001";
                   state<=x"1";
            end if;

            if  (clk_period_num>="00011") then
                  data_reg<=data_reg(11 downto 1) & mcp3201_dout;
            end if;
                   
       elsif (state=x"3") then
            mcp3201_ncs<='1';
            state<=x"0";
            mcp3201_ad_data<=data_reg;
       else
            mcp3201_ncs<='1';
            state<=x"0";
       end if ;
end if;
end if;
end process;
end arch_get_ad_mcp3201;

 

仿真时序图如下：

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