【设计工具】Virtex-5系统功耗设计的规则设计

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【设计工具】Virtex-5系统功耗设计的规则设计 [复制链接]

the past, ASSPs and ASICs often consumed the majority of power in system power
budgets. With the increase in FPGA performance, functions, and density, FPGA power
consumption is now a key design consideration and must meet certain industry
standards for maximum power allowed. For example, the communication industry
has a standard for the maximum power allowed per rack. GR-63-CORE, a standard
from Network Equipment Building Systems (NEBS), defines a power limit at shelf and
frame levels (e.g., 4 KW/rack), operational and non-operational temperature limits,
humidity range, and other environmental and safety levels for the equipment.
Because of these power limits, a product's functional density, such as ports per rack (in
networking equipment) can be limited by power consumption at the chassis, board, or
FPGA level. In addition, power consumption is also closely linked to thermal
consideration, which needs to be understood to keep the system working within its
temperature specifications of the various components. The reliability decreases as
parts are operated at higher temperatures, so keeping the temperature lower is also
important.

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