Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 200 mVat an output current of 250 mA for 3.3-volt option) and is directly proportional to the output current. Additionally,since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independentof output loading (typically 92 μA over the full range of output current, 0 mA to 250 mA). These two keyspecifications yield a significant improvement in operating life for battery-powered systems.The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also featuresa sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescentcurrent to less than 1 μA at TJ = 25°C.The TPS773xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS),or reset output voltage. The RESET output of the TPS773xx initiates a reset in DSP, microcomputer ormicroprocessor systems at power up and in the event of an undervoltage condition. An internal comparator inthe TPS773xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulatedoutput voltage. When OUT reaches 95% of its regulated voltage, RESET will go to a high-impedance state aftera 220-ms delay. RESET will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition)of its regulated voltage.For the TPS774xx, the power good terminal (PG) is an active high output, which can be used to implement apower-on reset or a low-battery indicator. An internal comparator in the TPS774xx monitors the output voltageof the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82%of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUTis above 82% of its regulated voltag
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