关于fpga的问题

ahhcj0716

关于fpga的问题 [复制链接]

我在看cyclone 3的用户手册，里面看到pll锁相环的关于programme duty cycle不是很懂什么意思

The programmable duty cycle allows PLLs to generate clock outputs with a variable
duty cycle. This feature is supported on the PLL post-scale counters. You can achieve
the duty cycle setting by a low and high time count setting for the post-scale counters.
The Quartus II software uses the frequency input and the required multiply or divide
rate to determine the duty cycle choices. The post-scale counter value determines the
precision of the duty cycle. The precision is defined by 50% divided by the post-scale
counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty
cycle choices between 5 to 90%.
Combining the programmable duty cycle with programmable phase shift allows the
generation of precise non-overlapping clocks.

有高手解释一下这是什么意思吗

eeleader

占空比周期的意思。

  方波的占空比是1.

  楼主给出英文表达了意思。PLL 输出的不仅频率可以编程，而且高低脉冲的宽度也可以改变！