有没有对于spi熟悉的大侠们，有几个问题要请教。标题要要彪悍……………………

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有没有对于spi熟悉的大侠们，有几个问题要请教。标题要要彪悍…………………… [复制链接]

  1.我对于spi接口内部的寄存器分布比较模糊，比如数据手册上说一共5个寄存器，SPICR1  SPICR2   SPISR   SPIBR  SPIDR。但是讲主从通信的时候又提到了移位寄存器shift register 和 各种 buffer。所以我不明白主从通信的时候用到的shift register里的数据是怎么进入那5个寄存器的。

     比如数据手册里有这么一段话：Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI Data Register after the last bit is shifted in.
     是不是这么理解的：shift register 既是 output buffer 又是 input buffer。等所有数据移入 shift register之后再进入了并行的SPIDR。不用人为操作了。

   但是这段话又让我晕了
    The main element of the SPI system is the SPI Data Register. The 8-bit data register in the master and the 8-bit data register in the slave are linked by theMOSI andMISO pins to form a distributed 16-bit register. When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the S-clock from the master, so data is exchanged between the master and the slave.
   上文中的“8-bit data register”是不是就是SPIDR呀，这个“8-bit data register”从文章看就是shift register。所以糊涂了。


      2.  有段话，数据手册上是这么写的，我看不太明白。
       4.4.2  CPHA = 0 Transfer Format
          The first edge on the SCK line is used to clock the first data bit of the slave into the master and the first  data bit of the master into the slave. In some peripherals, the first bit of the slave’s data is available at the  slave’s data out pin as soon as the slave is selected. In this format, the first SCK edge is issued a half cycle after SS has become low.
           那个clock……into……是怎么理解的？
           还有，大家都知道CPHA=0时，数据是再第1个边沿被采样的，这个采样是什么意思？是在第1个边沿采样然后就直接发出去了吗？

           A half SCK cycle later, the second edge appears on the SCK line.When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit.
           从这段话看，在第二个边沿发生时，先前在串行数据输入引脚（这个引脚是master的还是slave的？）锁存的值进入了寄存器，就是说第二个边沿是才进入了寄存器。（什么时候锁存了？）

          After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges.
           这段话我看的云里雾里的，第二个边沿之后，master的下一个bit从输出引脚发出，传到了slave 的输入引脚。这个之后怎么定义，是指第三个边沿还是指在第二个边沿和第三个边沿之间呢？



     3.Data written to the master SPI Data Register becomes the output data for the slave, and data read from the master SPI Data Register after a transfer operation is the input data from the slave.
       上文中写入master SPI Data Register的data是谁写入的，若spi接口连接了cpu和外设，是不是cpu写进去的还是外设写进去的？
        the output data for the slave 是指输出到slave的数据，还是slave的输出数据？
       data read from the master SPI Data Register after a transfer operation is the input data from the slave。意思是：CPU从master SPI Data Register读取的数据其实是master的输入，slave的输出吗？