VHDL中重载应该调用哪个库文件

gz475514589

VHDL中重载应该调用哪个库文件 [复制链接]

带控制端口的加法器，pout<=in1+in2;这条语句用到重载，不知道该调用那个库，求高手指导，谢谢

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lianxi4 is
port ( in1:in bit_vector;
       in2:in bit_vector;
      cnt1:bit;
      pout:out bit_vector
);
end lianxi4;
architecture func of lianxi4 is
begin
process(cnt1)
begin
  if(cnt1='1')then
pout<=in1+in2;
end if;
end process;
end func;

出现的错误：

Error (10327): VHDL error at lianxi4.vhdl(17): can't determine definition of operator ""+"" -- found 0 possible definitions
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
 Error: Peak virtual memory: 174 megabytes
 Error: Processing ended: Wed Jul 27 15:59:46 2011
 Error: Elapsed time: 00:00:02
 Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

gz475514589

自己顶下，谢谢

eeleader

in1,in2宽度未定义

gz475514589

定义了 in1和in2这两个位矢量后，仍然出现不能识别“+”的错误，编译器报错如下：
Error (10327): VHDL error at lianxi4.vhdl(17): can't determine definition of operator ""+"" -- found 0 possible definitions
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
        Error: Peak virtual memory: 174 megabytes
        Error: Processing ended: Thu Jul 28 10:02:35 2011
        Error: Elapsed time: 00:00:03
        Error: Total CPU time (on all processors): 00:00:02
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings
修改后的程序如下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lianxi4 is
port ( in1:in bit_vector(1 downto 0);--cichuwei2wei jiafaqi
       in2:in bit_vector(1 downto 0);
      cnt1:bit;
      pout:out bit_vector(1 downto 0)
);
end lianxi4;
architecture func of lianxi4 is
begin
process(cnt1)
begin
if(cnt1='1')then
pout<=in1+in2;
end if;
end process;
end func;

gz475514589

也就是 编译器不知道此处的“+”该如何操作。编译器不能识别这个“+”的意思