多个vhdl源文件编译出错，请求指点

gz475514589

多个vhdl源文件编译出错，请求指点 [复制链接]

此程序为以个全加器，
第一段代码：
library ieee;
use ieee.std_logic_1164.all;
entity h_adder is
port(a,b:in std_logic;
   co,so:out std_logic);
end h_adder;
architecture fh1 of h_adder is
begin
so<=a and(a nand b);
co<=not(a nand b);
end fh1;
第二段代码：
library ieee;
use ieee.std_logic_1164.all;
entity bianyi is
port(a,b:in std_logic;
   c:out std_logic);
end bianyi;
architecture f1 of bianyi is
begin
c<=a or b;
end f1;
第三段代码，用元件例化语句调用上面2个模块
library ieee;
use ieee.std_logic_1164.all;

entity f_adder is
port(ain,bin,cin:in std_logic;
   cout,sum:out std_logic);
end f_adder;

architecture yange of f_adder is
begin
component h_adder
port(a,b:in std_logic;
   co,so:out std_logic);
end component;

component bianyi
port(a,b:in std_logic;
      c:out std_logic);
end component;

signal d,e,f :std_logic;
begin
u1:h_adder port map(a=>ain,b=>bin,co=>d,so=>e);
u2:h_adder port map(a=>e,b=>cin,co=>f,so=>sum);
u3: bianyi port map(a=>d,b=>f,co=>cout);
end yange;

用元件例化语句调用其他两个源文件生成一个SCH图时出现错误，我反复查看没有找不出问题，
求各位大侠指点下，看时哪里错了，我首次把多个文件整合起来，谢谢。
出现的错误如下：
Error (10500): VHDL syntax error at f_adder.vhdl(11) near text "component";  expecting "end", or "(", or an identifier ("component" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at f_adder.vhdl(12) near text ":";  expecting ")", or ","
Error (10500): VHDL syntax error at f_adder.vhdl(17) near text ":";  expecting ")", or ","
Error (10500): VHDL syntax error at f_adder.vhdl(22) near text "begin";  expecting "end", or "(", or an identifier ("begin" is a reserved keyword), or a concurrent statement
Error: Quartus II Create Symbol File was unsuccessful. 4 errors, 0 warnings
Error: Peak virtual memory: 170 megabytes
Error: Processing ended: Wed Jul 27 15:05:05 2011
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:02