根据datasheet 见图1上面说的,XT1 外接的是32.768K的晶振,XT2接的是8M的晶振。 测试晶振是否起振用的是官网的例程,如下: // MSP-FET430P430 Demo - FLL+, Output 32kHz Xtal + HF Xtal + Internal DCO // // Description: This program demonstrates using an external 32kHz crystal to // supply ACLK, and using a high speed crystal or resonator to supply SMCLK. // MLCK for the CPU is supplied by the internal DCO. The 32kHz crystal // connects between pins Xin and Xout. The high frequency crystal or // resonator connects between pins XT2IN and XT2OUT. The DCO clock is // generated internally and calibrated from the 32kHz crystal. ACLK is // brought out on pin P1.5, SMCLK is brought out on P1.4, and MCLK is // brought out on pin P1.1. // ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz // //* An external watch crystal between XIN & XOUT is required for ACLK *// // // NOTE: External matching capacitors must be added for the high // speed crystal or resonator as required. // // MSP430F449 // ----------------- // /|\ | XIN|- // | | | 32kHz // ---|RST XOUT|- // | | // | | // | XT2IN|- // | | HF XTAL or Resonator (add capacitors) // | XT2OUT|- // | | // | P1.5|--> ACLK = 32kHz Crystal Out // | | // | P1.4|--> SMCLK = High Freq Xtal or Resonator Out // | | // | P1.1|--> MCLK = Default DCO Frequency // | | // | | // // G. Morton // Texas Instruments Inc. // Feb 2005 // Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A //***************************************************************************** #include <msp430x43x.h>
// Loop until 32kHz crystal stabilizes do { IFG1 &= ~OFIFG; // Clear oscillator fault flag for (i = 50000; i; i--); // Delay } while (IFG1 & OFIFG); // Test osc fault flag
FLL_CTL1 = SELS; // Select SMCLK source as XT2CLK P1DIR = 0x32; // Set P1.1,4,5 as outputs P1SEL = 0x32; // Select P1.1,4,5 as clocks
while(1); // Loop in place } 但是晶振一直不起振,我用内部的DCO就可以实现需要实现的功能,实在是无法解决了,希望大家帮忙解决下! 经过实际测试发现JTAG口的TD0、TD1、TMS 却出来的是8M的晶振。上传我自己画的原理图见图2