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17的datasheet上有专门的数据
IDD(REG)(3V3) regulator supply current
(3.3V)
active mode; code
while(1){}
executed from flash; all
peripherals disabled;
PCLK =
CCLKΔ8
CCLK=12MHz; PLL
disabled
[3][4]
-7-mA
CCLK=100MHz; PLL
enabled
[3][4]
-42-mA
CCLK=100MHz; PLL
enabled (LPC1759)
[3][5]
50
CCLK=120MHz; PLL
enabled (LPC1759)
[3][5]
-67-mA
Sleep mode [3][6]
-2-mA
Deep sleep mode [3][7]
-240- μA
Power-down mode [3][7]
-31- μA
Deep power-down mode;
RTC not running
[3]
-517-nA
IBAT battery supply currentDeep power-down mode;
RTC running
VDD(REG)(3V3) present
[8]
-134-nA
VDD(REG)(3V3) not
present
[9]
-
634-nA
IDD(IO) I/O supply currentDeep sleep mode [10]
-40-nA
Power-down mode [10]
-40-nA
Deep power-down mode [10]
-10-nA |
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