看看我的程序的警告：

shumin748646

看看我的程序的警告： [复制链接]

Warning (14130): Reduced register "current_state[7]~reg0" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "current_state[6]~reg0" with stuck data_in port to stuck value GND
Warning: Converted presettable and clearable register to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
 Warning (13310): Register "qout[4]" converted into equivalent circuit using register "qout[4]~_emulated" and latch "qout[4]~latch"
 Warning (13310): Register "qout[5]" converted into equivalent circuit using register "qout[5]~_emulated" and latch "qout[5]~latch"
 Warning (13310): Register "qout[3]" converted into equivalent circuit using register "qout[3]~_emulated" and latch "qout[3]~latch"
 Warning (13310): Register "qout[6]" converted into equivalent circuit using register "qout[6]~_emulated" and latch "qout[6]~latch"
 Warning (13310): Register "qout[7]" converted into equivalent circuit using register "qout[7]~_emulated" and latch "qout[7]~latch"
 Warning (13310): Register "qout[0]" converted into equivalent circuit using register "qout[0]~_emulated" and latch "qout[0]~latch"
 Warning (13310): Register "qout[1]" converted into equivalent circuit using register "qout[1]~_emulated" and latch "qout[1]~latch"
 Warning (13310): Register "qout[2]" converted into equivalent circuit using register "qout[2]~_emulated" and latch "qout[2]~latch"
Warning: Output pins are stuck at VCC or GND
 Warning (13410): Pin "oe_for_164245[0]" stuck at GND
 Warning (13410): Pin "oe_for_164245[1]" stuck at GND
 Warning (13410): Pin "oe_for_164245[2]" stuck at GND
 Warning (13410): Pin "oe_for_164245[3]" stuck at GND
 Warning (13410): Pin "current_state[6]" stuck at GND
 Warning (13410): Pin "current_state[7]" stuck at GND
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Warning: No exact pin location assignment(s) for 51 pins of 79 total pins
 Info: Pin current_state[0] not assigned to an exact location on the device
 Info: Pin current_state[1] not assigned to an exact location on the device
 Info: Pin current_state[2] not assigned to an exact location on the device
 Info: Pin current_state[3] not assigned to an exact location on the device
 Info: Pin current_state[4] not assigned to an exact location on the device
 Info: Pin current_state[5] not assigned to an exact location on the device
 Info: Pin current_state[6] not assigned to an exact location on the device
 Info: Pin current_state[7] not assigned to an exact location on the device
 Info: Pin tx_send not assigned to an exact location on the device
 Info: Pin cnt_tx[0] not assigned to an exact location on the device
 Info: Pin cnt_tx[1] not assigned to an exact location on the device
 Info: Pin cnt_tx[2] not assigned to an exact location on the device
 Info: Pin cnt_tx[3] not assigned to an exact location on the device
 Info: Pin cnt_tx[4] not assigned to an exact location on the device
 Info: Pin cnt_tx[5] not assigned to an exact location on the device
 Info: Pin cnt_tx[6] not assigned to an exact location on the device
 Info: Pin cnt_tx[7] not assigned to an exact location on the device
 Info: Pin dataout[0] not assigned to an exact location on the device
 Info: Pin dataout[1] not assigned to an exact location on the device
 Info: Pin dataout[2] not assigned to an exact location on the device
 Info: Pin dataout[3] not assigned to an exact location on the device
 Info: Pin dataout[4] not assigned to an exact location on the device
 Info: Pin dataout[5] not assigned to an exact location on the device
 Info: Pin dataout[6] not assigned to an exact location on the device
 Info: Pin dataout[7] not assigned to an exact location on the device
 Info: Pin rdsig not assigned to an exact location on the device
 Info: Pin frameerror not assigned to an exact location on the device
 Info: Pin trig_1 not assigned to an exact location on the device
 Info: Pin trig_2 not assigned to an exact location on the device
 Info: Pin trig_3 not assigned to an exact location on the device
 Info: Pin trig_4 not assigned to an exact location on the device
 Info: Pin trig_5 not assigned to an exact location on the device
 Info: Pin trig_6 not assigned to an exact location on the device
 Info: Pin trig_7 not assigned to an exact location on the device
 Info: Pin trig_8 not assigned to an exact location on the device
 Info: Pin trig_9 not assigned to an exact location on the device
 Info: Pin relay_not_act not assigned to an exact location on the device
 Info: Pin cnt_for_case[0] not assigned to an exact location on the device
 Info: Pin cnt_for_case[1] not assigned to an exact location on the device
 Info: Pin cnt_for_case[2] not assigned to an exact location on the device
 Info: Pin cnt_for_case[3] not assigned to an exact location on the device
 Info: Pin cnt_for_case_2[0] not assigned to an exact location on the device
 Info: Pin cnt_for_case_2[1] not assigned to an exact location on the device
 Info: Pin cnt_for_case_2[2] not assigned to an exact location on the device
 Info: Pin cnt_for_case_2[3] not assigned to an exact location on the device
 Info: Pin cnt_for_case_3[0] not assigned to an exact location on the device
 Info: Pin cnt_for_case_3[1] not assigned to an exact location on the device
 Info: Pin cnt_for_case_3[2] not assigned to an exact location on the device
 Info: Pin cnt_for_case_3[3] not assigned to an exact location on the device
 Info: Pin in_test not assigned to an exact location on the device
 Info: Pin relay_not_act_te not assigned to an exact location on the device
Warning: Found 65 output pins without output pin load capacitance assignment
 Info: Pin "clk_500k" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "ale" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "oe" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "add[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "add[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "add[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "tx" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "oe_for_164245[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "oe_for_164245[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "oe_for_164245[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "oe_for_164245[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "current_state[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "current_state[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "current_state[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "current_state[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "current_state[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "current_state[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "current_state[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "current_state[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "tx_send" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "relay[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "relay[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "relay[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "relay[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_tx[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_tx[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_tx[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_tx[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_tx[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_tx[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_tx[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_tx[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "dataout[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "dataout[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "dataout[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "dataout[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "dataout[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "dataout[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "dataout[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "dataout[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "rdsig" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "frameerror" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "in" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "trig_1" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "trig_2" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "trig_3" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "trig_4" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "trig_5" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "trig_6" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "trig_7" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "trig_8" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "trig_9" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "relay_not_act" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case_2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case_2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case_2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case_2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case_3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case_3[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case_3[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
 Info: Pin "cnt_for_case_3[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Warning: Following 6 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
 Info: Pin oe_for_164245[0] has GND driving its datain port
 Info: Pin oe_for_164245[1] has GND driving its datain port
 Info: Pin oe_for_164245[2] has GND driving its datain port
 Info: Pin oe_for_164245[3] has GND driving its datain port
 Info: Pin current_state[6] has GND driving its datain port
 Info: Pin current_state[7] has GND driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Warning: Timing Analysis is analyzing one or more combinational loops as latches
 Warning: Node "qout[4]~latch" is a latch
 Warning: Node "qout[6]~latch" is a latch
 Warning: Node "qout[0]~latch" is a latch
 Warning: Node "qout[3]~latch" is a latch
 Warning: Node "qout[1]~latch" is a latch
 Warning: Node "qout[2]~latch" is a latch
Warning: Can't find clock settings "clk" in current project -- ignoring clock settings
Warning: Found combinational loop of 2 nodes
 Warning: Node "qout[7]~latch"
 Warning: Node "qout[7]~362"
Warning: Found combinational loop of 2 nodes
 Warning: Node "qout[5]~latch"
 Warning: Node "qout[5]~358"
Warning: Found 24 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
 Info: Detected gated clock "WideOr2~167" as buffer
 Info: Detected gated clock "qout[3]~5" as buffer
 Info: Detected gated clock "WideOr2~168" as buffer
 Info: Detected gated clock "Decoder0~1119" as buffer
 Info: Detected gated clock "Decoder0~1125" as buffer
 Info: Detected gated clock "rtl~4" as buffer
 Info: Detected gated clock "Decoder0~1127" as buffer
 Info: Detected gated clock "rtl~1" as buffer
 Info: Detected gated clock "Decoder0~1117" as buffer
 Info: Detected gated clock "rtl~2" as buffer
 Info: Detected gated clock "rtl~5" as buffer
 Info: Detected gated clock "Decoder0~1113" as buffer
 Info: Detected gated clock "Decoder0~1118" as buffer
 Info: Detected gated clock "Decoder0~1124" as buffer
 Info: Detected gated clock "rtl~3" as buffer
 Info: Detected gated clock "rtl~0" as buffer
 Info: Detected ripple clock "current_state[5]~reg0" as buffer
 Info: Detected ripple clock "current_state[4]~reg0" as buffer
 Info: Detected ripple clock "clk_500k_reg" as buffer
 Info: Detected ripple clock "current_state[0]~reg0" as buffer
 Info: Detected ripple clock "current_state[1]~reg0" as buffer
 Info: Detected ripple clock "current_state[2]~reg0" as buffer
 Info: Detected ripple clock "current_state[3]~reg0" as buffer
 Info: Detected ripple clock "clkout_urat" as buffer
Warning: Circuit may not operate. Detected 98 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.

该怎么解决呢？

芝锐

疯狂啊

常见泽1

新版主？

shilaike

大厉害了。。。竟然这么多警告。。。。

哈哈。。LZ不用惊慌，只要没错就OK。。。。。。