//******************************************************************************
// MSP-FET430P440 Demo - FLL+ Output 32k xtal + HF xtal + internal DCO
//
// Description This program demostrates using an external 32khz crystal to
// supply the internal ACLK, and using a high speed crystal or resonator to
// supply SMCLK. The MLCK for the CPU is supplied by the XT2. The 32khz
// crystal connects to pins Xin and Xout. The high frequency crystal or
// resonator connects to pins XT2in and XT2out. The DCO clock is generated
// internally and calibrated by the 32khz crystal. The resulting ACLK is
// brought out on I/O pin P1.5, SMCLK is brought out on P1.4, and MCLK is
// brought out on I/O pin P1.1.
// Note:
// External matching capacitors must be added for the high speed crystal or
// resonator as required.
//
// MSP430F449
// -----------------
// /|\ | XIN|-
// | | | 32kHz
// ---|RST XOUT|-
// | |
// | |
// | XT2IN|-
// | | HF XTAL or resonator (add capacitors)
// | XT2OUT|-
// | |
// | P1.5|--> ACLK = 32khz crystal out:32K
// | |
// | P1.4|--> SMCLK = high freq xtal or resonator out:4M
// | |
// | P1.1|--> MCLK = XT2 frequency :1M???
// | |
// | |
//
// B. Merritt
// Texas Instruments Inc.
// October 2003
// Built with IAR Embedded Workbench Version: 1.26B
// January 2004
// Updated for IAR Embedded Workbench Version: 2.21B
//******************************************************************************
#include "msp430x44x.h"
void main(void)
{
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // stop watchdog timer
FLL_CTL0|= DCOPLUS+XCAP18PF;
FLL_CTL1 = FLL_CTL1 & ~XT2OFF; // clear bit = high freq xtal on
SCFI0 |= FN_4; // x2 DCO freq, 8MHz nominal DCO
SCFQCTL = 120; // (120+1) x 32768 x 2 = 8 MHz
do // loop until flag is clear
{
FLL_CTL0 = FLL_CTL0 & ~XT2OF; // clear high freq oscillator fault flag
for (i = 50000; i; i--); // delay for crystal to start and FLL to lock
}
while (FLL_CTL0 & XT2OF); // test high freq oscillator fault flag
// if flag remained clear then -
FLL_CTL1|= SELS+SELM_XT2; // switch SMCLK = HF xtal
P1DIR = 0x32; // P1.1, P1.4 & P1.5 to outputs
P1SEL = 0x32; // P1.1, P1.4 & P1.5 functions to output
// MCLK, SMCLK & ACLKm
while(1); // loop in place
}