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引用:
谢谢指导,我会一句一句的消化理解的。不过如果有相关的例子,那就太好了。
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;*******************************************************************************
; MSP430xG461x Demo - DMA2, Rpt'd ××k to DAC1, 8-Bit Sine, TBCCR2, DCO
;
; Description: DMA2 is used to transfer a sine look-up ta××e byte-by-byte
; as a repeating ××ock to DAC12_1. The effect is a sine w××e output. Timer_B
; operates in upmode with CCR2 loading DAC12_1 on the rising edge, CCR2_CCIFG
; triggering the next DMA2 transfer. Use external reference on VeRef+.
; ACLK = 32kHz, MCLK = SMCLK = TBCLK = default DCO 1048576Hz
;
; MSP430xG461x
; -----------------
; /|\| XIN|-
; | | | 32kHz
; --|RST XOUT|-
; | |
; Ext Ref->|VeRef+ DAC1/P6.7|--> ~ 1kHz sine w××e output
;
;
; A. Dannenberg/ K.Venkat
; Texas Instruments Inc.
; Dec 2006
; Built with IAR Embedded Workbench Version: 3.41A
;*******************************************************************************
#include "msp430xG46x.h"
;-------------------------------------------------------------------------------
RSEG CSTACK ; Define stack segment
;-------------------------------------------------------------------------------
RSEG CODE ; Assem××e to Flash memory
;-------------------------------------------------------------------------------
RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop watchdog timer
SetupDMA2 movx.a #Sin_tab,&DMA2SA ; Source ××ock address
movx.a #DAC12_1DAT,&DMA2DA ; Destination single address
mov.w #020h,&DMA2SZ ; ××ock size
mov.w #DMA2TSEL_2,&DMACTL0 ; DAC12IFG trigger
mov.w #DMASBDB+DMADT_4+DMASRCINCR_3+DMAEN,&DMA2CTL; Rpt, inc src, byte-byte
SetupDAC12 mov.w #DAC12SREF_2+DAC12RES+DAC12LSEL_3+DAC12IR+DAC12AMP_5+DAC12ENC,&DAC12_1CTL
;
SetupC1 mov.w #OUTMOD_7,&TBCCTL2 ; Reset/set
mov.w #01,&TBCCR2 ; PWM Duty Cycle
SetupC0 mov.w #032-1,&TBCCR0 ; Clock period of TBCCR0
SetupTB mov.w #TBSSEL_2+MC_1,&TBCTL ; SMCLK, up mode
;
Mainloop bis.b #CPUOFF,SR ; Enter LPM0
nop ; Needed only for debugger
;
;-------------------------------------------------------------------------------
; 8-bit Sine Lookup ta××e with 32 steps
;-------------------------------------------------------------------------------
Sin_tab DB 128, 152, 176, 198, 218, 234, 245, 253
DB 255, 253, 245, 234, 218, 198, 176, 152
DB 128, 103, 79, 57, 37, 21, 10, 2
DB 0, 2, 10, 21, 37, 57, 79, 103
;-------------------------------------------------------------------------------
COMMON INTVEC ; Interrupt Vectors
;-------------------------------------------------------------------------------
ORG RESET_VECTOR ; POR, ext. Reset, Watchdog
DW RESET
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