本帖最后由 dontium 于 2015-1-23 13:24 编辑 我在用5509作开发。接着仿真器调试程序时,可以响应中断。但是如果把程序烧写进flash后,主程序可以正常运行,就是不能响应中断。我用了外部中断0和1。下面是我主程序初始化和中断设定部分:
extern Uint32 myvec;
interrupt void myIsrInt0();
interrupt void myIsrInt1();
.
.
.
void main( )
{
/*初始化CSL库*/
CSL_init();
/*EMIF为全EMIF接口*/
CHIP_RSET(XBSR,0x0a01);
/*设置系统的运行速度为144MHz*/
PLL_config(&myConfig);
/*初始化DSP的EMIF*/
EMIF_config(&emiffig);
IRQ_globalDisable();
IRQ_setVecs((Uint32)(&myvec));
IRQ_plug(IRQ_EVT_INT0,&myIsrInt0);
IRQ_clear(IRQ_EVT_INT0);
IRQ_plug(IRQ_EVT_INT1,&myIsrInt1);
IRQ_clear(IRQ_EVT_INT1);
.
.
.
}
下面是中断向量表。这是我从TI例子中找的,稍微改了一下。
.def _myvec
.sect \".vectors\"
.ref _c_int00
.ref _myIsrInt0
.ref _myIsrInt1
.def no_isr
.vli_off
;**********************************************************************************
; .sect \"vecTable\"
;**********************************************************************************
_myvec:
RST: .ivec _c_int00, USE_RETA
NMI: .ivec no_isr ; SINT1
INT0: .ivec _myIsrInt0 ; SINT2
INT2: .ivec no_isr ; SINT3
TINT0: .ivec no_isr ; SINT4
RINT0: .ivec no_isr ; SINT5
RINT1: .ivec no_isr ; SINT6
XINT1: .ivec no_isr ; SINT7
SINT8: .ivec no_isr ; SINT8
DMAC1: .ivec no_isr ; SINT9
DSPINT: .ivec no_isr ; SINT10
INT3: .ivec no_isr ; SINT11
RINT2: .ivec no_isr ; SINT12
XINT2: .ivec no_isr ; SINT13
DMAC4: .ivec no_isr ; SINT14
DMAC5: .ivec no_isr ; SINT15
INT1: .ivec _myIsrInt1 ; SINT16
XINT0: .ivec no_isr ; SINT17
DMAC0: .ivec no_isr ; SINT18
INT4: .ivec no_isr ; SINT19
DMAC2: .ivec no_isr ; SINT20
DMAC3: .ivec no_isr ; SINT21
TINT1: .ivec no_isr ; SINT22
INT5: .ivec no_isr ; SINT23
BERR: .ivec no_isr ; SINT24
DLOG: .ivec no_isr ; SINT25
RTOS: .ivec no_isr ; SINT26
SINT27: .ivec no_isr ; SINT27
SINT28: .ivec no_isr ; SINT28
SINT29: .ivec no_isr ; SINT29
SINT30: .ivec no_isr ; SINT30
SINT31: .ivec no_isr ; SINT31
.vli_on
.text
no_isr: B no_isr
cmd文件也是从TI例子中找的,稍微改动了一下。
-stack 0x400
-sysstack 0x400
-priority
-llnkrtdx.a55l
-ldrivers.a55l /* device drivers support */
-lcsl5509x.lib
-lrts55x.lib /* C and C++ run-time library support */
-lclki.a55l
-lrts55.lib
MEMORY
{
PAGE 0:
MMR : origin = 0000000h, length = 00000c0h
SPRAM : origin = 00000c0h, length = 0000040h
VECS : origin = 0000100h, length = 0000100h
DARAM0 : origin = 0000200h, length = 000600h
DARAM1 : origin = 0000800h, length = 0001800h
DARAM2 : origin = 0002000h, length = 000e000h
SARAM0 : origin = 0010000h, length = 0005000h
SARAM1 : origin = 0015000h, length = 0004000h
SARAM2 : origin = 0019000h, length = 0003000h
SARAM3 : origin = 001c000h, length = 0004000h
SARAM4 : origin = 0020000h, length = 0004000h
SARAM5 : origin = 0024000h, length = 0004000h
SARAM6 : origin = 0028000h, length = 0004000h
SARAM7 : origin = 002c000h, length = 0004000h
SARAM8 : origin = 0030000h, length = 0004000h
SARAM9 : origin = 0034000h, length = 0004000h
SARAM10 : origin = 0038000h, length = 0004000h
SARAM11 : origin = 003c000h, length = 0004000h
SARAM12 : origin = 0040000h, length = 0004000h
SARAM13 : origin = 0044000h, length = 0004000h
SARAM14 : origin = 0048000h, length = 0004000h
SARAM15 : origin = 004c000h, length = 0004000h
CE0 : origin = 0050000h, length = 03b0000h
CE1 : origin = 0400000h, length = 0400000h
CE2 : origin = 0800000h, length = 0400000h
CE3 : origin = 0c00000h, length = 03f8000h
PDROM : origin = 0ff8000h, length = 07f00h
/* VECS : origin = 0ffff00h, length = 00100h */ /* reset vector */
}
SECTIONS
{
.vectors : {} > VECS PAGE 0 /* interrupt vector table */
.cinit : {} > SARAM0 PAGE 0
.text : {} > SARAM1 PAGE 0
.stack : {} > DARAM1 PAGE 0
.sysstack: {} > DARAM1 PAGE 0
.sysmem : {} > DARAM2 PAGE 0
.cio : {} > DARAM2 PAGE 0
.data : {} > DARAM2 PAGE 0
.bss : {} > DARAM2 PAGE 0
.const : {} > DARAM2 PAGE 0
.csldata: {} > DARAM1 PAGE 0
/*dmaMem: {} > DARAM0 PAGE 0*/
}
请高手指点一下,是不是还要设定其他的东西,或者哪里写得有问题,谢谢!!