/******/
ScibRegs.SCICCR.all=0x07; //SCI通信控制寄存器
/*
bit 7 0: STOP BITS 一个结束位
bit 6 0: parity 奇极性
bit 5 0: parity enable 禁止极性功能
bit 4 0: loop back ena 禁止回送测试模式功能
bit 3 0: addr/idle mode 选择空闲线协议
bit 2 1: 字符长度8
bit 1 1: 字符长度8
bit 0 1: 字符长度8
*/
/******/
ScibRegs.SCICTL1.all=0x03; //SCI控制寄存器1
/*
bit 7 0: reserved
bit 6 0: rx err int ena
bit 5 0: sw reset
bit 4 0: reserved
bit 3 0: tx wake
bit 2 0: sleep
bit 1 1: tx ena
bit 0 1: rx ena
*/
/******/
ScibRegs.SCICTL2.all=0x00; //SCI控制寄存器2
/*
bit15-8 ; reserved
bit 7 0: TXRDY
bit 6 0: TX EMPTY
bit 5 0: Reserved
bit 4 0: Reserved
bit 3 0: Reserved
bit 2 0: Reserved
bit 1 1: RS/BK INT ENA
bit 0 1: TX INT ENA
ScibRegs.SCICTL1.all=0x23;
// PieCtrlRegs.PIEIER9.bit.INTx3 = 1; // Enable SCIRXINT in PIE group 9
// PieCtrlRegs.PIEIER9.bit.INTx4 = 1; // Enable SCITXINT in PIE group 9
// IER |= 0x0100; // Enable INT9 in IER to enable PIE group 9