High Performance 32-Bit MCU 80 MHz, 1.56 DMIPS/MHz CPU core Single cycle multiply and divide hardware Flash pre-fetch module, 256Byte cache Fast context switch and interrupt response USB device/host/OTG with dedicated DMA 4 ch. hardware DMA controller Atomic bit manipulation
The MIPS32® M4K™ core from MIPS® Technologies is a member of the MIPS32 M4K™ processor core family. It is a highperformance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor. It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products. The M4K core is ideally positioned to support new products for emerging segments of the routing, network access, network storage, residential gateway, and smart mobile device markets. It is especially well-suited for microcontroller and hardware accelerator applications, as well as systems requiring multiple cores, when high performance density is critical. The synthesizable M4K core implements the MIPS32 Release 2 Architecture with the MIPS16e™ ASE.The Memory Management Unit (MMU) consists of a simple, Fixed Mapping Translation (FMT) mechanism for applications that do not require the full capabilities of a Translation Lookaside Buffer (TLB) based MMU. The core includes two different Multiply/ Divide Unit (MDU) implementations, selectable at build-time, allowing the implementor to trade off performance and area. The high-performance MDU option that implements single cycle 32x16-bit MAC instructions or two cycle 32x32-bit, which enable DSP algorithms to be performed efficiently. The area-efficientMDUoption handles multiplies with a one-bit-per-clock iterative algorithm. The M4K core is cacheless; in lieu of caches, it includes a simple interface to SRAM-style devices. This interface may be configured for independent instruction and data devices or combined into a unified interface.The SRAM interface allows deterministic response, while still maintaining high performance. An optional Enhanced JTAG (EJTAG) block allows for single-stepping of the processor as well as instruction and data virtual address/value breakpoints. Additionally, real-time tracing of instruction program counter, data address, and data values can be supported.
第3方的证据，证实了上面的说法： jbb -> RE: How to obtain 1.5 DMIPS/MHz ? (Apr. 24, 2008 2:45:52 AM)
Hi,
Thanks for your comments. I have continued my tests with the Dhrystone code with the following setting: - code running in Flash - 24MHz with 0 wait states I have found around 36 DMIPS, that is 1.5 DMIPS/MHz. This is in line with the number announced.
But...by reading carefully different documents about Dhrystone tests, it appears that the functions "inlining" must be disabled.
So I have re-do my measures without the inline mode and the performance fall down to approx 1.29 DMIPS/MHz. I have also tested the 16-bit instructions option and I have measured less than 0.9 DMIPS/MHz (with no inline mode).
It would be helpfull for me if someone can confirm my results. 数据来自microchip 论坛： http://forum.microchip.com/printable.aspx?m=322135
一些解释： 1.relative equivalance DMIPS/MHz指的是：“without the inline mode and the performance fall down to approx 1.29 DMIPS/MHz”。 这意味着，M4K的1.56DMIPS/MHz是因为使用了inline模式，不使用inline模式时M4K为约1.29DMIPS/MHz；而CortexM3的1.25DMIPS/MHz是在未使用inline模式下得到的。
2.but with double the code size of CortexM3...指的是：M4K的约1.29DMIPS/MHz是通过32位模式得到的，因此它的代码大小（大约）是CortexM3的2倍。另外，M4K使用16位模式时为：less than 0.9 DMIPS/MHz (with no inline mode)
MIPS: Million Instructions executed Per Second,每秒百万条指令,用来计算同一秒内系统的处理能力 DMIPS:Dhrystone Million Instructions executed Per Second ：主要用于测整数计算能力。 MFLOPS:主要用于测浮点计算能力。
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