请高手指点一下关于时序仿真的问题？

尚水云者

请高手指点一下关于时序仿真的问题？ [复制链接]

用verilog写的异步置位清零的D触发器：
module asyn_d (
        clk,
        clr,
        set,
        d,
        q
);

//input signal
input clk;
input clr,set;
input d;

//output signal
output q;

//declare the type of data
reg q;

//logic relationship
always @(posedge clk or posedge clr or posedge set)
        begin
                if(clr)     //if clr is high level,then reset 'q'
                        begin q <= 1'b0; end
                else         //if clr is loe level,then..
                if(set)
                        begin q <=1'b1; end
                else        
                        begin q <= d; end
        end
endmodule        
Quartus ii 9.0功能仿真结果：

功能仿真警告：Warning: Found clock-sensitive change during active clock edge at time 75.0 ns on register "|asyn_d|q~reg0"
时序仿真：
http://bbs.dicder.com/data/attac ... 9nzisrvfp27vlsf.jpg
时序仿真没有产生警告，为什么时序仿真时错误的？
整体编译结果：
Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
        Warning (13310): Register "q~reg0" is converted into an equivalent circuit using register "q~reg0_emulated" and latch "q~reg0latch"
Warning: No exact pin location assignment(s) for 5 pins of 5 total pins
        Info: Pin q not assigned to an exact location on the device
        Info: Pin set not assigned to an exact location on the device
        Info: Pin clr not assigned to an exact location on the device
        Info: Pin d not assigned to an exact location on the device
        Info: Pin clk not assigned to an exact location on the device
Warning: Found 1 output pins without output pin load capacitance assignment
        Info: Pin "q" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Warning: Timing Analysis is analyzing one or more combinational loops as latches
        Warning: Node "q~reg0latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
        Info: Assuming node "clk" is an undefined clock
请高手指点……

eeleader

Clk,Clr,Set 都是边沿触发.  异步信号, 我认为这样可能造成时序分析出错!

 

解决办法:Clk,Clr 做边沿触发就可以了

         

walkerinsky

这个跟FPGA的D触发器结构有关系的。新的ALTERA的FPGA里的D触发器是异步复位同步清零的结构。所以对你的代码，综合后是一个跟器件相关的行为，这个在BEHAVIOR仿真中是看不到的。建议参考QUARTUS 手册里面的CODE STYLE里面对D触发器的描述，同时看看器件的CELL单元结构。

尚水云者

多谢斑竹哦！

尚水云者

呵呵 同学

eeleader

期待LZ最后验证的结果!