--将1khz的标准信号std_clk分成周期为2秒的占空比为50%的CE输出 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY freq_division_1 IS PORT(std_clk,reset:IN STD_LOGIC; CE:OUT STD_LOGIC); END freq_division_1; ARCHITECTURE freq_division_1_str OF freq_division_1 IS BEGIN PROCESS(std_clk,reset) VARIABLE count:INTEGER RANGE 0 TO 999; VARIABLE flag:INTEGER RANGE 0 TO 1; BEGIN IF(reset='0') THEN count:=0; CE<='1'; flag:=0; ELSIF (std_clk'EVENT AND std_clk='1') THEN IF(count=999) THEN IF(flag=0) THEN CE<='0'; ELSE CE<='1'; END IF; flag:=(flag+1)MOD 2; count:=0; ELSE count:=count+1; END IF; END IF; END PROCESS; END freq_division_1_str