Accurately measuring ADC driving-circuit settling time

安_然

Accurately measuring ADC driving-circuit settling time [复制链接]

Many modern data acquisition systems consist of highspeed,
high-resolution ADCs.1 CMOS-switched, capacitorbased
ADCs are often chosen for such designs due to their
low cost and low power dissipation. These ADCs use an
unbuffered front end directly coupled to the sampling
network. To effectively minimize noise and signal distortion,
it is necessary to drive the ADC with a high-speed, lownoise,
low-distortion operational amplifier.2 To achieve
minimal distortion it is important for the op amp output to
settle to the desired accuracy within the acquisition time
of the ADC. Normally the op amp settling time is either
calculated from the frequency response specified in the
datasheet or measured by probing the output with an
oscilloscope that has a limitation on resolution. Sometimes
the difference between the op amp input and output is
amplified to achieve better accuracy. These methods are
limited by the oscilloscope resolution or circuit parasitic.
Moreover, the settling time of the op amp is affected by
the parasitic capacitance and inductance introduced by
the oscilloscope probe. In another method, the difference
between output and input is amplified to increase the
resolution of the measurement. None of these methods
includes the parasitic capacitance and inductance present
in the ADC sampling circuit and package