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大家好,我用DC对我的设计逻辑综合后,在modelsim中进行后仿真。我先对某个路径进行时序检查,得到下面结果: dc_shell-t> report_timing -delay min -to ref_frame_array_u/w_addr_reg_9_/D
**************************************** Report : timing -path full -delay min -max_paths 1 Design : ME_and_MC Version: V-2004.06-SP2 Date : Sun Jul 25 12:51:16 2010 ****************************************
# A fanout number of 1000 was used for high fanout net computations.
Operating Conditions: typical Library: typical Wire Load Model Mode: top
Startpoint: ref_frame_array_u/w_addr_reg_9_ (rising edge-triggered flip-flop clocked by clk) Endpoint: ref_frame_array_u/w_addr_reg_9_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min
Des/Clust/Port Wire Load Model Library ------------------------------------------------ ME_and_MC tsmc18_wl40 typical
Point Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ref_frame_array_u/w_addr_reg_9_/CK (DFFRX1) 0.00 # 0.00 r ref_frame_array_u/w_addr_reg_9_/Q (DFFRX1) 0.55 0.55 f ref_frame_array_u/add_27/A[9] (ref_frame_array_DW01_inc_13_0) 0.00 0.55 f ref_frame_array_u/add_27/U1_1_9/S (ADDHXL) 0.40 0.95 f ref_frame_array_u/add_27/SUM[9] (ref_frame_array_DW01_inc_13_0) 0.00 0.95 f ref_frame_array_u/U61/Y (AND2X2) 0.23 1.19 f ref_frame_array_u/w_addr_reg_9_/D (DFFRX1) 0.00 1.19 f data arrival time 1.19
clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock uncertainty 0.10 0.10 ref_frame_array_u/w_addr_reg_9_/CK (DFFRX1) 0.00 0.10 r library hold time -0.06 0.04 data required time 0.04 -------------------------------------------------------------------------- data required time 0.04 data arrival time -1.19 -------------------------------------------------------------------------- slack (MET) 1.14 此报告显示,这段路径没有hold_time violation。然后,我将.v网表和.sdf文件以及stand_cell的.v文件导入modelsim进行时序仿真,会出现下面的违例报告: # ** Error: /export/home/st5/h.264/sim/tsmc18.v(7692): $hold( posedge CK &&& (flag == 1):5095 ns, negedge D:5095 ns, 500 ps ); # Time: 5095 ns Iteration: 2 Instance: :me_tb:ME_and_MC_u:ref_frame_array_u:w_addr_reg_9_ 因此,比较迷惑,现在请教大家,该如何处理这类问题。下面是我从.sdf文件中截取的w_addr_reg_9_的时序信息: (CELL (CELLTYPE "DFFRX1") (INSTANCE ref_frame_array_u/w_addr_reg_9_) (DELAY (ABSOLUTE (IOPATH (posedge CK) Q (0.805:0.805:0.805) (0.553:0.553:0.553)) (IOPATH (negedge RN) Q () (0.460:0.460:0.460)) (IOPATH (posedge CK) QN (0.771:0.771:0.771) (0.663:0.663:0.663)) (IOPATH (negedge RN) QN (0.680:0.680:0.680) ()) ) ) (TIMINGCHECK (WIDTH (posedge CK) (0.129:0.129:0.129)) (WIDTH (negedge CK) (0.177:0.177:0.177)) (SETUP (posedge D) (posedge CK) (0.077:0.077:0.077)) (SETUP (negedge D) (posedge CK) (0.157:0.160:0.160)) (HOLD (posedge D) (posedge CK) (-0.058:-0.059:-0.059)) (HOLD (negedge D) (posedge CK) (-0.055:-0.059:-0.059)) (SETUP (posedge RN) (posedge CK) (0.058:0.058:0.058)) (HOLD (posedge RN) (posedge CK) (-0.038:-0.038:-0.038)) (WIDTH (negedge RN) (0.192:0.192:0.192)) ) ) 下面是stand_cell的.v文件中DFFRX1的描述: `timescale 1ns/1ps `celldefine module DFFRX1 (Q, QN, D, CK, RN); output Q, QN; input D, CK, RN; reg NOTIFIER; supply1 xSN;
buf XX0 (xRN, RN); buf IC (clk, CK); udp_dff I0 (n0, D, clk, xRN, xSN, NOTIFIER); and I4 (flag, xRN, xSN); buf I1 (Q, n0); not I2 (QN, n0);
specify specparam tplh$RN$Q = 1.0, tphl$RN$Q = 1.0, tplh$RN$QN = 1.0, tphl$RN$QN = 1.0, tplh$CK$Q = 1.0, tphl$CK$Q = 1.0, tplh$CK$QN = 1.0, tphl$CK$QN = 1.0, tsetup$D$CK = 1.0, thold$D$CK = 0.5, tsetup$RN$CK = 1.0, thold$RN$CK = 0.5, tminpwl$RN = 1.0, tminpwl$CK = 1.0, tminpwh$CK = 1.0;
if (flag) (posedge CK *> (Q +: D)) = (tplh$CK$Q, tphl$CK$Q); if (flag) (posedge CK *> (QN -: D)) = (tplh$CK$QN, tphl$CK$QN); $setuphold(posedge CK &&& (flag == 1), posedge D, tsetup$D$CK, thold$D$CK, NOTIFIER); $setuphold(posedge CK &&& (flag == 1), negedge D, tsetup$D$CK, thold$D$CK, NOTIFIER); (negedge RN *> (Q +: 1'b0)) = (tphl$RN$Q); (negedge RN *> (QN -: 1'b0)) = (tplh$RN$QN); $setuphold(posedge CK, posedge RN, tsetup$RN$CK, thold$RN$CK, NOTIFIER); $width(negedge RN, tminpwl$RN, 0, NOTIFIER); $width(negedge CK &&& (flag == 1), tminpwl$CK, 0, NOTIFIER); $width(posedge CK &&& (flag == 1), tminpwh$CK, 0, NOTIFIER);
endspecify endmodule // DFFRX1 `endcelldefine 大家看看,该如何处理这里问题啊!
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