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一粒金砂(初级)

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在嵌入式系统中处理器和操作系统在处理中断时分别作了什么工作? [复制链接]

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Hardware/Software Interrupt Sequence 1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to the processor if an asserted interrupt is not masked. 3. The processor acknowledges the INTR and responds with an interrupt acknowledge cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host bridge. This command is broadcast over PCI by the ICH8. 4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH8 converts it into the two cycles that the internal 8259 pair can respond to. Each cycle appears as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers. 5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set and the corresponding IRR bit is reset. On the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. The slave controller uses these bits to determine if it must respond with an interrupt vector during the second INTA# pulse. 6. Upon receiving the second internally generated INTA# pulse, the PIC returns the interrupt vector. If no interrupt request is present because the request was too short in duration, the PIC returns vector 7 from the master controller. 7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine.  详情 回复 发表于 2007-9-4 12:35
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一粒金砂(初级)

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Hardware/Software Interrupt Sequence
1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or
seen high in level mode, setting the corresponding IRR bit.
2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.
3. The processor acknowledges the INTR and responds with an interrupt acknowledge
cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host
bridge. This command is broadcast over PCI by the ICH8.
4. Upon observing its own interrupt acknowledge cycle on PCI, the ICH8 converts it
into the two cycles that the internal 8259 pair can respond to. Each cycle appears
as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded
interrupt controllers.
5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR
bit is set and the corresponding IRR bit is reset. On the trailing edge of the first
pulse, a slave identification code is broadcast by the master to the slave on a
private, internal three bit wide bus. The slave controller uses these bits to
determine if it must respond with an interrupt vector during the second INTA#
pulse.
6. Upon receiving the second internally generated INTA# pulse, the PIC returns the
interrupt vector. If no interrupt request is present because the request was too
short in duration, the PIC returns vector 7 from the master controller.
7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of
the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate
EOI command is issued at the end of the interrupt subroutine.
 
 

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