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买了块2410的板子,上面用cs8900驱动网口。这几天把cs8900配置了一下,现在8900在产生中断时,可以通过自己的IRQ0脚触发2410的EINT9脚。但8900在收到包的时候只能产生一次中断,也就是说收到第一个包8900会在IRQ0脚产生中断电平,并在IRQ(120h)中断寄存器队列中设置RXEvent(124h)寄存器的值。但收到二个包时,8900只会在IRQ(120h)中设置RXEvent(124h)的值,不会产生中断电平。
2410采用高电平中断,我在中断管脚用万用表量的电平,确实是8900收到第二个包时没有产生高电平。收到第二个包时,可以收到包中的内容。
具体代码如下:
IMPORT HandleIRQ
AREA Init,CODE,READONLY
ENTRY
b ResetHandler
b .
b .
b .
b .
b .
b HandlerIRQ
b HandlerFIQ
LTORG
ResetHandler
mrs r0,cpsr ; set the cpu to SVC32 mode
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr_c,r0
ldr sp,=SVCStack ;Setup SVC mode's pc
ldr r0,=WTCON ;watch dog disable
ldr r1,=0x0
str r1,[r0]
ldr r0,=INTMSK ;all interrupt disable
ldr r1,=0xffffffff
str r1,[r0]
ldr r0,=INTSUBMSK ;all sub interrupt disable
ldr r1,=0x7ff
str r1,[r0]
ldr r0,=INTMOD ;Set Int Mode as IRQ
ldr r1,=0
str r1,[r0]
;setup system clock
ldr r0,=LOCKTIME
ldr r1,=0x00ffffff
str r1,[r0]
ldr r0,=MPLLCON
ldr r1,=((161<<12)+(3<<4)+1)
str r1,[r0]
ldr r0,=CLKDIVN
ldr r1,=0x3
str r1,[r0]
;Setup SDRAM
ldr r0,=SMRDATA
ldr r1,=BWSCON ;BWSCON Address
add r2,r0,#52 ;End address of SMRDATA
0
ldr r3,[r0],#4
str r3,[r1],#4
cmp r2,r0
bne %B0
ldr r0,=GPFCON ; Led_Display
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x10
str r1,[r0]
;Setup UART0
ldr r0,=GPHCON ; Config GPH as UART
ldr r1,=0xaa
str r1,[r0]
ldr r0,=UFCON0
ldr r1,=0
str r1,[r0]
ldr r0,=UMCON0
ldr r1,=0
str r1,[r0]
ldr r0,=ULCON0
ldr r1,=0x3
str r1,[r0]
ldr r0,=UCON0
ldr r1,=0x45
str r1,[r0]
ldr r0,=UBRDIV0
ldr r1,=26
str r1,[r0]
;setup CS8900
ldr r0,=0x1900030a ;set packet page pointer to 0x116
ldr r1,=0x3116
strh r1,[r0]
ldr r0,=0x1900030c ;change bus mode to memory mode
ldr r1,=0x8417
strh r1,[r0]
ldr r0,=0x18000022 ;use IRQ0
ldr r1,=0x0000
strh r1,[r0]
ldr r0,=0x18000158 ;set MAC
ldr r1,=0x1412
strh r1,[r0]
ldr r0,=0x1800015a
ldr r1,=0x1816
strh r1,[r0]
ldr r0,=0x1800015c
ldr r1,=0x1c1a
strh r1,[r0]
ldr r0,=0x18000112 ;set LineCtl to enable RX and TX
ldr r1,=0x00d3
strh r1,[r0]
ldr r0,=0x18000102 ;set RXCfg to enable RX Done Interupt
ldr r1,=0x3903
strh r1,[r0]
ldr r0,=0x18000104 ;set RXCtl to recieve Individual and Broadcast Addr
ldr r1,=0x3d05
strh r1,[r0]
;Setup EINT9
ldr r0,=GPGCON ; Config GPG1 as EINT9
ldr r1,=0x08
str r1,[r0]
ldr r0,=EXTINT1 ; config EINT9 as high level
ldr r1,=0x10
str r1,[r0]
;clear all the interupts
ldr r0,=EINTPEND ;clear External INT Reg
ldr r1,=0x200
str r1,[r0]
ldr r0,=SRCPND ;Clear SRCPND
ldr r1,=0xffffffff
str r1,[r0]
ldr r0,=SUBSRCPND ;Clear SUBSRCPND
ldr r1,=0x7ff
str r1,[r0]
ldr r0,=INTPND ;Clear INTPND
ldr r1,=0xffffffff
str r1,[r0]
;Setup Stack Pointer
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack
orr r1,r0,#USERMODE
mov r1,r0
and r1,r0,#0xffffff7f ;Open IRQ INT
msr cpsr_cxsf,r1 ;USRMode
ldr sp,=UserStack
;open interupt
ldr r0,=EINTMASK ; clear mask for EINT9
ldr r1,=0x00fffdf0
str r1,[r0]
ldr r0,=INTMSK ;Open Uart0, timer4 and EINT
ldr r1,=0xEFFFBFCF
str r1,[r0]
ldr r0,=INTSUBMSK ;Open Uart0 Sub Int
ldr r1,=0x7f8
str r1,[r0]
IMPORT __main
b __main
HandlerIRQ
stmfd sp!,{r0-r12,lr}
ldr r0,=INTMSK ;all interrupt disable
ldr r1,=0xffffffff
str r1,[r0]
ldr r0,=INTSUBMSK ;all sub interrupt disable
ldr r1,=0x7ff
str r1,[r0]
bl HandleIRQ
ldr r0,=EINTPEND ;clear External INT Reg
ldr r1,=0x200
str r1,[r0]
ldr r0,=SRCPND ;Clear SRCPND
ldr r1,=0xffffffff
str r1,[r0]
ldr r0,=SUBSRCPND ;Clear SUBSRCPND
ldr r1,=0x7ff
str r1,[r0]
ldr r0,=INTPND ;Clear INTPND
ldr r1,=0xffffffff
str r1,[r0]
ldr r0,=INTMSK ;Open Uart0, timer4 and EINT
ldr r1,=0xEFFFBFCF
str r1,[r0]
ldr r0,=INTSUBMSK ;Open Uart0 Sub Int
ldr r1,=0x7f8
str r1,[r0]
ldmfd sp!,{r0-r12,lr}
subs pc,lr,#4
void PrintChar(unsigned char tmp)
{
URXH0 = tmp;
}
void delay(int tmp)
{
unsigned int i;
int loop =1000;
for (;tmp>0; --tmp)
{
for (i = 0; i < loop; ++i);
}
}
void PrintStr(char * Str)
{
unsigned int i;
i = 0;
for (i = 0; 1; ++i)
{
if ('\0' == Str) return;
while(!(rUTRSTAT0 & 0x2));
delay(10);
PrintChar(Str);
}
}
void CheckEtherEngine()
{
}
void SendPacket(void *Data, size_t Length)
{
unsigned short BusState = 0;
unsigned short *Addr = (unsigned short *)Data;
unsigned short Tmp;
(*(volatile unsigned short*)0x18000144) = 0x00c9; /*TXCMD*/
(*(volatile unsigned short*)0x18000146) = (unsigned short)Length; /*TXLEN*/
do
{
BusState = (*(volatile unsigned short*)0x18000138);
delay(100);
}while (0 == (BusState & 0x0100));
for (; Length > 0; Length -= 2)
(*(volatile unsigned short*)0x18000a00) = *Addr++;
}
__value_in_regs struct __initial_stackheap __user_initial_stackheap(
unsigned R0, unsigned SP, unsigned R2, unsigned SL)
{
struct __initial_stackheap config;
config.heap_base = 0x33000000;/*(int)&Image$$ZI$$Limit;*/
config.stack_base = SP;
return config;
}
int main()
{
unsigned short Tmp = 0;
unsigned short i = 0;
unsigned Length;
unsigned char ARPPacket[] = {
0xff,0xff,0xff,0xff,0xff,0xff,
0x12,0x14,0x16,0x18,0x1a,0x1c,
0x08,0x06,
0x00,0x01,0x08,0x00,0x06,0x04,0x00,0x01,
0x12,0x14,0x16,0x18,0x1a,0x1c,
0xc0,0xa8,0x00,0x06,
0x00,0x00,0x00,0x00,0x00,0x00,
0xc0,0xa8,0x00,0x01
};
CheckEtherEngine();
while (1)
{
SendPacket(ARPPacket, 44);
delay(2000);
/*
do
{
Tmp = (*(volatile unsigned short*)0x18000120);
delay(10);
}while (0 == Tmp);
Length = (*(volatile unsigned short*)0x18000402);
for (i = 0; i < Length / 2; i++)
{
Tmp = (*(volatile unsigned short*)(0x18000404 + i));
if (Tmp == 0) PrintStr("Packet Rcved!\n");
}
*/
}
while(1);
return 0;
}
void HandleIRQ()
{
unsigned char IntSrc = *(volatile unsigned char *)0x4a000014;/*Interupt Offset Register*/
unsigned short Tmp;
unsigned short Length,i,Status,IntValue;
switch (IntSrc)
{
case 28:
break;
case 14:
break;
case 5:
IntValue = (*(volatile unsigned short*)0x18000120);
if (0x0004 == (IntValue & 0x000f))
{
Status = (*(volatile unsigned short*)0x18000400);
Length = (*(volatile unsigned short*)0x18000402);
for (i = 0; i < Length; i+=2)
{
Tmp = (*(volatile unsigned short*)(0x18000404));
}
Tmp = (*(volatile unsigned short*)0x18000124);
}
break;
default:
break;
}
}
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