----------------------------------------------------
entity frequencydivider is
Port ( clk : in STD_LOGIC;
clk_div2 : out STD_LOGIC;
clk_div4 : out STD_LOGIC;
clk_div8 : out STD_LOGIC);
end frequencydivider;
architecture Behavioral of frequencydivider is
signal count : std_logic_vector(3 downto 0) ;--= "0000";
begin
process(clk)
begin
if(clk'event and clk ='1')then
if(count = "1111") then
count <= (others => '0');
else
count <= count + 1;
end if;
end if;
end process;
clk_div2 <= count(0)after 20ns;
clk_div4 <= count(1) after 20ns;
clk_div8 <= count(2) after 20ns;
end Behavioral;
----------------------------------------------------
请问在用波形测试的时候为什么结果为U 和X 呢
warning信息:Warning: There is an 'U'|'X'|'W'|'Z'|'-'
in an arithmetic operand, the result will be 'X'(es).