我的程序中有7组双向端口,1组8位,用到了7个高阻态,这时quartusII就提示
Error: Design requires 7 output enable signals, but the device can contain only 6 output enable signals
我用的EPM3128ATC100-10,不换芯片怎么解决这个问题
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY pc104 IS
PORT (data: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); --pin 85, 84, 83, 81, 80, 79, 77, 76
data_dir: out std_logic;
dir: INOUT STD_LOGIC_VECTOR (5 DOWNTO 0); --dir
inputflag: IN STD_LOGIC; --pin 88
outputflag: IN STD_LOGIC; --pin 90
rst: in std_logic; --pin 87
addr: IN STD_LOGIC_VECTOR (3 DOWNTO 0); --pin 97, 96, 94, 93
dio: INOUT STD_LOGIC_VECTOR (47 DOWNTO 0)); --DIO0~DIO7
END pc104;
ARCHITECTURE pc104a OF pc104 IS
SIGNAL data_in: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_out: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL tmp: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
send:PROCESS (addr, inputflag, data, dir)
variable flag: boolean;
BEGIN
data_in <= data;
if(rst = '0' and rst'event) then
flag := true;
else
flag := false;
end if;
IF (addr = "1100" and inputflag = '0') THEN
dir(4 downto 0) <= data_in(4 downto 0);
dir(5) <= data_in(4);
elsif(flag) then
dir <= "000000";
end if;
if (dir(0) = '1') then
if(addr = "0011" and inputflag = '0') then
dio(7 downto 0) <= data_in;
end if;
else
dio(7 downto 0) <= "ZZZZZZZZ";
end if;
if (dir(1) = '1') then
if(addr = "0100" and inputflag = '0') then
dio(15 downto 8) <= data_in;
end if;
else
dio(15 downto 8) <= "ZZZZZZZZ";
end if;
if (dir(2) = '1') then
if(addr = "0101" and inputflag = '0') then
dio(23 downto 16) <= data_in;
end if;
else
dio(23 downto 16) <= "ZZZZZZZZ";
end if;
if (dir(3) = '1') then
if(addr = "0110" and inputflag = '0') then
dio(31 downto 24) <= data_in;
end if;
else
dio(31 downto 24) <= "ZZZZZZZZ";
end if;
if (dir(4) = '1') then
if(addr = "0111" and inputflag = '0') then
dio(39 downto 32) <= data_in;
end if;
else
dio(39 downto 32) <= "ZZZZZZZZ";
end if;
if (dir(5) = '1') then
if(addr = "1000" and inputflag = '0') then
dio(47 downto 40) <= data_in;
end if;
else
dio(47 downto 40) <= (others => 'Z');
end if;
END PROCESS send;
receive:PROCESS(addr, outputflag, dio, dir)
BEGIN
if(outputflag = '0') then
if (addr = "0011" AND dir(0) = '0') THEN
data_out <= dio(7 DOWNTO 0);
elsif (addr = "0100" and dir(1) = '0') THEN
data_out <= dio(15 DOWNTO 8);
elsif (addr = "0101" AND dir(2) = '0') THEN
data_out <= dio(23 DOWNTO 16);
elsif (addr = "0110" AND dir(3) = '0') THEN
data_out <= dio(31 DOWNTO 24);
elsif (addr = "0111" AND dir(4) = '0') THEN
data_out <= dio(39 DOWNTO 32);
elsif (addr = "1000" AND dir(5) = '0') THEN
data_out <= dio(47 DOWNTO 40);
end if;
end if;
END PROCESS receive;
process(data_out, outputflag)
begin
if(outputflag = '0') then
data <= data_out;
else
data <= (others => 'Z');
end if;
end process;