Internal ERAM and Port P0,P2,WR,RD I/O
Question
If I have the ERAM enabled (default) and I only access the first 2048 bytes of memory using a MOVX do the P0 P2 WR and RD lines ever change?
Answer
MOVX access to RAM address location below the value entered in AUXR register XRS field will access the internal RAM provided of course EXTRAM bit is cleared in AUXR too. In such cases, the Port0 and Port2 will not be exercised, nor the RD and Wr output. All the above is true for any MOVX : MOVX @Ri or MOVX @DPTR
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发表于 2008-6-28 17:44
Internal ERAM and Port P0,P2,WR,RD I/O
Question
If I have the ERAM enabled (default) and I only access the first 2048 bytes of memory using a MOVX do the P0 P2 WR and RD lines ever change?
Answer
MOVX access to RAM address location below the value entered in AUXR register XRS field will access the internal RAM provided of course EXTRAM bit is cleared in AUXR too. In such cases, the Port0 and Port2 will not be exercised, nor the RD and Wr output. All the above is true for any MOVX : MOVX @Ri or MOVX @DPTR