The ARM926EJ-S core includes a 16-Kbyte level 1 (L1) cache system,
a 6 × 3 multi-layer AHB crossbar switch, and a 16 channel DMA
ARM926EJ-S microprocessor core
— 16K instruction cache and 16K data cache
— High-performance ARM? 32-bit RISC engine
— Thumb? 16-bit compressed instruction set for a leading level of code density