The rate of VCLK signal depends on the CLKVAL field in the LCDCON1 register. Table 15-3 defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 0.
VCLK(Hz) = HCLK/[(CLKVAL+1)x2]
The frame rate is VSYNC signal frequency. The frame rate is related with the field of VSYNC, VBPD, VFPD,LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, and CLKVAL in LCDCON1 and LCDCON2/3/4 registers. Most LCD drivers need their own adequate frame rate. The frame rate is calculated as follows:
VFRAME=HCLK/[(CLKVAL+1)x2]/{(VSPW+1+VBPD+1+LCD_YSIZE_TFT+VFPD+1)*(HSPW+1+HSPD+1+HFPD+1+LCD_XSIZE_TFT)}
LZ回去还是好好查下datasheet吧!
引用 5 楼 xilidecai 的回复:
The rate of VCLK signal depends on the CLKVAL field in the LCDCON1 register. Table 15-3 defines the relationship of VCLK and CLKVAL. The minimum value of CLKVAL is 0.
VCLK(Hz) = HCLK/[(CLKVAL+1)x2]
The frame rate is VSYNC signal frequency. The frame rate is related with the field of VSYNC, VBPD, VFPD,LINEVAL, HSYNC, HBPD, HFPD, HOZVAL, and CLKVAL in LCDCON1 and LCDCON2/3/4 registers. Most LCD drivers need their own adequate frame rate. The frame rate is calculated as follows:
VFRAME=HCLK/[(CLKVAL+1)x2]/{(VSPW+1+VBPD+1+LCD_YSIZE_TFT+VFPD+1)*(HSPW+1+HSPD+1+HFPD+1+LCD_XSIZE_TFT)}
LZ回去还是好好查下datasheet吧!