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Priciples of Verifiable RTL Design, 2nd Ed.
by Lionel Bening & Harry Foster
Writing Testbenches, Functional Verification of HDL Models
by Janick Bergeron
A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog
(HDL Chip Design) by Douglas J. Smith |
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