状态机kzq程序:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY kzq IS
PORT( X: IN STD_LOGIC;
MR,MY,MG,CR,CY,CG: OUT STD_LOGIC;
C60,C20,C4:OUT STD_LOGIC);
END kzq;
ARCHITECTURE behv OF kzq IS
TYPE SET IS (MGCR,MYCR,MRCG,MRCY);
SIGNAL current_state, next_state,last_state: SET;
BEGIN
REG:PROCESS(X) --X为上升沿,状态跳转
BEGIN
IF X='1' AND X'EVENT THEN
last_state <= current_state;
current_state <= next_state;
END IF;
END PROCESS;
COM:PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN MGCR => next_state <= MYCR;
MY<='1';CR<='1';MG<='0';MR<='0';CG<='0';CY<='0'; --主黄乡红
C4 <='1';C20<='0';C60<='0';--倒计时4秒
WHEN MYCR => next_state <=MRCG;
MR <='1';CG<='1';MY<='0';MG<='0';CR<='0';CY<='0'; --主红乡绿
C20<='1';C4 <='0';C60<='0';--倒计时20秒
WHEN MRCG => next_state <=MRCY;
MR <='1';CY<='1'; MG<='0';MY<='0';CG<='0';CR<='0';--主红乡黄
C4<='1';C60<='0';C20<='0';--倒计时4秒
WHEN MRCY=> next_state <=MGCR;
MG <='1';CR<='1';MR <='0';MY<='0';CY<='0'; CG<='0';--主绿乡红
C60<='1';C4 <='0';C20<='0';--倒计时60秒
END CASE;
END PROCESS;
END behv;
控制状态机时序信号的程序XH:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY XH IS
PORT( S: IN STD_LOGIC;
C20_1:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
C20_2:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
C4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
MR,MY,MG,CR,CY,CG: IN STD_LOGIC;
CO:OUT STD_LOGIC);
END XH;
ARCHITECTURE behav OF XH IS
BEGIN
PROCESS(S,C20_1,C20_2,C4,MR,MY,MG,CR,CY,CG)
BEGIN
IF (MG='1')AND(CR='1')AND(MR='0')AND(MY='0')AND(CY='0')AND(CG='0')AND(S='1')
THEN CO <='1';
ELSE CO <='0';
END IF;
IF (MY='1')AND(CR='1')AND(MR='0')AND(MG='0')AND(CY='0')AND(CG='0')AND(C4="0000")
THEN CO <='1';
ELSE CO <='0';
END IF;
IF (MR='1')AND(CG='1')AND(MY='0')AND(MG='0')AND(CR='0')AND(CY='0')AND(S='0')
THEN CO <='1';
ELSE CO <='0';
END IF;
IF (MR='1')AND(CG='1')AND(MY='0')AND(MG='0')AND(CR='0')AND(CY='0')AND(C20_1="0000")AND(C20_2="0000")
THEN CO<='1';
ELSE CO <='0';
END IF;
IF (MR='1')AND(CY='1')AND(MY='0')AND(MG='0')AND(CR='0')AND(CG='0')AND(C4="0000")
THEN CO <='1';
ELSE CO <='0';
END IF;
END PROCESS;
END behav;
倒计时4的程序:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity countdown4 is
port(clk,en:in std_logic;
cq:out std_logic_vector(3 downto 0)
);
end countdown4;
architecture behav of countdown4 is
signal cql:std_logic_vector(3 downto 0);
begin
cq<=cql;
process(clk)
begin
if clk'event and clk='1' then
if en='1' then cql<=cql-1;
end if;
if cql=0 then cql<="0011";
end if;
end if;
end process;
end behav;
倒计时20的程序:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity countdown20 is
port(clk,en:in std_logic;
cq1:out std_logic_vector(3 downto 0);
cq2:out std_logic_vector(3 downto 0)
);
end countdown20;
architecture behav of countdown20 is
signal cql:std_logic_vector(3 downto 0);
signal cqh:std_logic_vector(3 downto 0);
begin
cq2<=cqh;
cq1<=cql;
process(clk)
begin
if clk'event and clk='1' then
if en='1' then
if cql=0 then cql<="1001";cqh<=cqh-1;
else cql<=cql-1;
end if;
if cqh=0 and cql=0 then cqh<="0001";cql<="1001";
end if;
end if;
end if;
end process;
end behav;
倒计时60程序:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity countdown60 is
port(clk,en:in std_logic;
cq3:out std_logic_vector(3 downto 0);
cq4:out std_logic_vector(3 downto 0)
);
end countdown60;
architecture behav of countdown60 is
signal cql:std_logic_vector(3 downto 0);
signal cqh:std_logic_vector(3 downto 0);
begin
cq4<=cqh;
cq3<=cql;
process(clk)
begin
if clk'event and clk='1' then
if en='1' then
if cql=0 then cql<="1001";cqh<=cqh-1;
else cql<=cql-1;
end if;
if cqh=0 and cql=0 then cqh<="0101";cql<="1001";
end if;
end if;
end if;