问题究竟出现在哪儿呢?堆栈太小?0x1a00不小了吧?退出中断时,也开中断了啊
中断响应代码如下,红色部分为中断执行部分
void HandlerUsbd(void)
{
U8 usbdIntpnd,epIntpnd;
U8 saveIndexReg=pUDCreg->INDEX;
pINTreg->rINTMSK |=BIT_USBD; //close usbd interrupt
ClearPending(BIT_USBD);//clear interrput
EdbgOutputDebugString ( "usb_interrupt!\r\n");
usbdIntpnd=pUDCreg->UIR;
epIntpnd=pUDCreg->EIR;
if(usbdIntpnd&SUSPEND_INT)
{
pUDCreg->UIR=SUSPEND_INT;
EdbgOutputDebugString( "SUSPEND_INT\r\n");
}
if(usbdIntpnd&RESUME_INT)
{
pUDCreg->UIR=RESUME_INT;
EdbgOutputDebugString("RESUME_INT\r\n");
}
if(usbdIntpnd&RESET_INT)
{
pUDCreg->UIR=RESET_INT; //RESET_INT should be cleared after ResetUsbd().
EdbgOutputDebugString( "RESET_INT\r\n");
ReconfigUsbd();
PrepareEp1Fifo();
}
if(epIntpnd&EP0_INT)
{
EdbgOutputDebugString( "EP0_INT\r\n");
pUDCreg->EIR=EP0_INT;
Ep0Handler();
}
if(epIntpnd&EP1_INT)
{
EdbgOutputDebugString( "EP1_INT\r\n");
pUDCreg->EIR=EP1_INT;
Ep1Handler();
}
if(epIntpnd&EP2_INT)
{
pUDCreg->EIR=EP2_INT;
EdbgOutputDebugString( "EP2_INT\r\n"); //not implemented yet
//Ep2Handler();
}
if(epIntpnd&EP3_INT)
{
EdbgOutputDebugString( "EP3_INT\r\n");
pUDCreg->EIR=EP3_INT;
Ep3Handler();
}
if(epIntpnd&EP4_INT)
{
EdbgOutputDebugString( "EP4_INT\r\n");//not implemented yet
pUDCreg->EIR=EP4_INT;
//Ep4Handler();
}
pUDCreg->INDEX=saveIndexReg;
pINTreg->rINTMSK &=~ (BIT_USBD); //open usbd interrupt
}
void ReconfigUsbd(void)
{
// *** End point information ***
// EP0: control
// EP1: bulk in end point
// EP2: not used
// EP3: bulk out end point
// EP4: not used
DbgPrintf("reconfigusbd start!\r\n");
pUDCreg->PMR=PWR_REG_DEFAULT_VALUE; //disable suspend mode
pUDCreg->INDEX=0;
pUDCreg->MAXP=FIFO_SIZE_8; //EP0 max packit size = 8
pUDCreg->EP0ICSR1=EP0_SERVICED_OUT_PKT_RDY|EP0_SERVICED_SETUP_END;
//EP0:clear OUT_PKT_RDY & SETUP_END
pUDCreg->INDEX=1;
#if (EP1_PKT_SIZE==32)
pUDCreg->MAXP=FIFO_SIZE_32; //EP1:max packit size = 32
#else
pUDCreg->MAXP=FIFO_SIZE_64; //EP1:max packit size = 64
#endif
pUDCreg->EP0ICSR1=EPI_FIFO_FLUSH|EPI_CDT;
pUDCreg->ICSR2=EPI_MODE_IN|EPI_IN_DMA_INT_MASK|EPI_BULK; //IN mode, IN_DMA_INT=masked
pUDCreg->OCSR1=EPO_CDT;
pUDCreg->OCSR2=EPO_BULK|EPO_OUT_DMA_INT_MASK;
pUDCreg->INDEX=2;
pUDCreg->MAXP=FIFO_SIZE_64; //EP2:max packit size = 64
pUDCreg->EP0ICSR1=EPI_FIFO_FLUSH|EPI_CDT|EPI_BULK;
pUDCreg->ICSR2=EPI_MODE_IN|EPI_IN_DMA_INT_MASK; //IN mode, IN_DMA_INT=masked
pUDCreg->OCSR1=EPO_CDT;
pUDCreg->OCSR2=EPO_BULK|EPO_OUT_DMA_INT_MASK;
pUDCreg->INDEX=3;
#if (EP3_PKT_SIZE==32)
pUDCreg->MAXP=FIFO_SIZE_32; //EP3:max packit size = 32
#else
pUDCreg->MAXP=FIFO_SIZE_64; //EP3:max packit size = 64
#endif
pUDCreg->EP0ICSR1=EPI_FIFO_FLUSH|EPI_CDT|EPI_BULK;
pUDCreg->ICSR2=EPI_MODE_OUT|EPI_IN_DMA_INT_MASK; //OUT mode, IN_DMA_INT=masked
pUDCreg->OCSR1=EPO_CDT;
//clear OUT_PKT_RDY, data_toggle_bit.
//The data toggle bit should be cleared when initialization.
pUDCreg->OCSR2=EPO_BULK|EPO_OUT_DMA_INT_MASK;
pUDCreg->INDEX=4;
pUDCreg->MAXP=FIFO_SIZE_64; //EP4:max packit size = 64
pUDCreg->EP0ICSR1=EPI_FIFO_FLUSH|EPI_CDT|EPI_BULK;
pUDCreg->ICSR2=EPI_MODE_OUT|EPI_IN_DMA_INT_MASK; //OUT mode, IN_DMA_INT=masked
pUDCreg->OCSR1=EPO_CDT;
//clear OUT_PKT_RDY, data_toggle_bit.
//The data toggle bit should be cleared when initialization.
pUDCreg->OCSR2=EPO_BULK|EPO_OUT_DMA_INT_MASK;
pUDCreg->EIR=EP0_INT|EP1_INT|EP2_INT|EP3_INT|EP4_INT;
pUDCreg->UIR=RESET_INT|SUSPEND_INT|RESUME_INT;
//EP0,1,3 & reset interrupt are enabled
pUDCreg->EIER=EP0_INT|EP1_INT|EP3_INT;
pUDCreg->UIER=RESET_INT;
//ep0State=EP0_STATE_INIT;
pINTreg->rSRCPND = pINTreg->rSRCPND; // clear all interrupt
pINTreg->rINTPND = pINTreg->rINTPND; // clear all interrupt
DbgPrintf("reconfigusbd end!\r\n");
}
void PrepareEp1Fifo(void)
{
int i;
U8 in_csr1;
pUDCreg->INDEX=1;
in_csr1=pUDCreg->EP0ICSR1;
for(i=0;i
ep1Buf=(U8)(transferIndex+i);
WrPktEp1(ep1Buf,EP1_PKT_SIZE);
SET_EP1_IN_PKT_READY();
DbgPrintf("PrepareEp1Fifo ing \r\n");
}