#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
OS_CPU_SR cpu_sr;
#endif
OS_ENTER_CRITICAL();
i2cint = 0;
iicSt = rIICSTAT;
if(iicSt & 0x8){
I2C_end = 0xFF;
rIICCON = 0xaf;
ClearPending(BIT_IIC);
return;
} //When bus arbitration is failed.clear pending bit
if(iicSt & 0x4){ClearPending(BIT_IIC);} //When a slave address is matched with IICADD
if(iicSt & 0x2){ClearPending(BIT_IIC);} //When a slave address is 0000000b
if(iicSt & 0x1){
if(I2C_num >0 ){
rIICSTAT = iicSt&(~(1<<5));
rIICCON = 0x2f;
Delay(1);
//OSSemPost(I2cFail);
ClearPending(BIT_IIC);
return;
} //When ACK isn't received and iic data hasn't transmitted over
}
switch(_iicMode)
{
case POLLACK:
i2stat = iicSt; //-- return the status register value
// OSSemPost(I2cSucc);
i2cint = 1;/////////---
i2cnum = I2C_num;
break;
case RDDATA:
I2C_num--;
if(I2C_num == -1){
rIICSTAT = 0x90; //Stop MasRx condition
//rIICCON = 0xaf; //Resumes IIC operation.
rIICCON = 0x2f;
Delay(1); //Wait until stop condtion is in effect.
i2cint = 2; ///---
i2cnum = I2C_num;
OSSemPost(I2cSucc);
break;
}
*pI2C_buf++ = rIICDS;
if(I2C_num==0){ //no data to be send
rIICCON = 0x2f; //Resumes IIC operation with NOACK.
i2cint = 3;///---
i2cnum = I2C_num;
}else{
rIICCON = 0xaf; //Resumes IIC operation with ACK
i2cint = 4;///---
i2cnum = I2C_num;
}
break;
case WRDATA:
if(I2C_suba_en ==0){ //-- two word address both transmitted
if((I2C_num--)==0){
rIICSTAT = 0xd0; //Stop MasTx condition
rIICCON = 0xaf; //-- writer 0 to IICCON[4] to clear the int pend,resuming IIC operation (this also assert the ack enable and rx/tx int enable)
Delay(1); //Wait until stop condtion is in effect.
//The pending bit will not be set after issuing stop condition.
I2C_end = TRUE;
OSSemPost(I2cSucc);
i2cint = 5;///---
i2cnum = I2C_num;
break;
}else{
rIICDS = *pI2C_buf++;
//for(i=0;i<10;i++);
rIICCON = 0xaf; //-- writer 0 to IICCON[4] to clear the int pend,resuming IIC operation (this also assert the ack enable and rx/tx int enable)
i2cint = 6;///---
i2cnum = I2C_num;
break;
}
}
if(I2C_suba_en ==4){ //-- writer mode:write first word address
rIICDS = I2C_subaH;
//for(i=0;i<10;i++); //-- for setup time until rising edge of IICSCL
rIICCON = 0xaf; //-- writer 0 to IICCON[4] to clear the int pend,resuming IIC operation (this also assert the ack enable and rx/tx int enable)
I2C_suba_en--; //-- I2C_suba_en = 2,indicate that first word address has been transmitted.
i2cint = 7;///---
i2cnum = I2C_num;
break;
}
if(I2C_suba_en ==3){ //-- write second word address
rIICDS = I2C_subaL;
// for(i=0;i<10;i++);
rIICCON = 0xaf; //-- writer 0 to IICCON[4] to clear the int pend,resuming IIC operation (this also assert the ack enable and rx/tx int enable)
I2C_suba_en = 0; //-- second word address transmitted,I2C_suba_en ==0
i2cint = 8;///---
i2cnum = I2C_num;
break;
}
case SETRDADDR:
if(I2C_suba_en ==2){ //--to read data,first ,write word address to EEPROM
rIICDS = I2C_subaH;
//for(i=0;i<10;i++); //-- for setup time until rising edge of IICSCL
Delay(1);
rIICCON = 0xaf; //-- writer 0 to IICCON[4] to clear the int pend,resuming IIC operation (this also assert the ack enable and rx/tx int enable)
I2C_suba_en--; //-- I2C_suba_en = 2,indicate that first word address has been transmitted.
i2cint = 9;///---
i2cnum = I2C_num;
break;
}
if(I2C_suba_en ==1){ //-- ??????????word???????·
rIICDS = I2C_subaL;
//for(i=0;i<10;i++); //-- for setup time until rising edge of IICSCL
rIICCON = 0xaf; //-- writer 0 to IICCON[4] to clear the int pend,resuming IIC operation (this also assert the ack enable and rx/tx int enable)
I2C_suba_en = 0; //-- I2C_suba_en = 2,indicate that first word address has been transmitted.
i2cint = 10;///---
i2cnum = I2C_num;
break;
}
if(I2C_suba_en ==0){ //-- read mode:two 8-bit word addressess write completed
rIICDS = I2C_sla+1;
rIICSTAT = 0xb0; //MasRx,Start
rIICCON = 0xaf; //Resumes IIC operation.
I2C_suba_en = -1;
i2cint = 11;///---
i2cnum = I2C_num;
break;
}
if(I2C_suba_en == -1){ //-- read mode:two 8-bit word addressess write completed
_iicMode = RDDATA; //-- set iic operation mode flag to read
rIICCON = 0xaf; //Resumes IIC operation with ACK.
i2cint = 12;///---
i2cnum = I2C_num;
break;
}
default:
rIICCON = 0x2f;
i2cint = 14;///---
i2cnum = I2C_num;
break;
}
//================================
ClearPending(BIT_IIC);
//================================
OS_EXIT_CRITICAL();
}
if(iicSt & 0x8){
I2C_end = 0xFF;
rIICCON = 0xaf;
ClearPending(BIT_IIC);
return;
} //When bus arbitration is failed.clear pending bit
if(iicSt & 0x4){ClearPending(BIT_IIC);} //When a slave address is matched with IICADD
if(iicSt & 0x2){ClearPending(BIT_IIC);} //When a slave address is 0000000b
if(iicSt & 0x1){//-- 没有收到返回
if(I2C_num >0 ){
rIICSTAT = iicSt&(~(1<<5));
rIICCON = 0x2f;
Delay(1);
//OSSemPost(I2cFail);
ClearPending(BIT_IIC);
return;
} //When ACK isn't received and iic data hasn't transmitted over
}
switch(_iicMode)
{
case POLLACK:
i2stat = iicSt; //-- return the status register value
// OSSemPost(I2cSucc);
i2cint = 1;/////////---
i2cnum = I2C_num;
break;