arm922T mmu问题，bootloader贴出来了，那位大虾能帮忙看一下问题在哪儿？

limengsz

arm922T mmu问题，bootloader贴出来了，那位大虾能帮忙看一下问题在哪儿？ [复制链接]

AREA    Init, CODE, READONLY
         CODE32
; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later


I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled
NO_INT          EQU     0xC0 ; Mask used to disable interrupts (Both FIR and IRQ)
ENABLE_INT      EQU     0x3f ; enable IRQ and FIQ interrupt


Len_FIQ_Stack    EQU     0x800
Len_IRQ_Stack    EQU     0x800
Len_ABT_Stack    EQU     0x100
Len_UND_Stack    EQU     0x100
Len_SVC_Stack    EQU     0x800   ;this is Pseudotarget

top_of_stacks    EQU     0x00300000

; Add lengths >0 for FIQ_Stack, ABT_Stack, UND_Stack if you need them.
; Offsets will be loaded as immediate values.
; Offsets must be 8 byte aligned.
;TOP_Stack_Addr         EQU  0x00300000

Offset_FIQ_Stack         EQU     0x100
Offset_IRQ_Stack         EQU     Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack         EQU     Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack         EQU     Offset_ABT_Stack + Len_ABT_Stack
Offset_SVC_Stack         EQU     Offset_UND_Stack + Len_UND_Stack


; --- CP15_Register_1:Control register
MMU_Control_M   EQU     0x1  ; Enable mmu
MMU_Control_A EQU0x2      ; Enable address alignment faults
MMU_Control_C  EQU0x4      ; Enable data cache
MMU_Control_W EQU0x8      ; Enable write-buffer
MMU_Control_P  EQU0x10     ; Compatability: 32 bit code
MMU_Control_D  EQU0x20     ; Compatability: 32 bit data
MMU_Control_L  EQU0x40     ; Compatability:
MMU_Control_B  EQU0x80     ; Enable Big-Endian
MMU_Control_S  EQU0x100    ; Enable system protection
MMU_Control_R  EQU0x200    ; Enable ROM protection
MMU_Control_I  EQU0x1000   ; Enable Instruction cache
MMU_Control_X  EQU0x2000   ; Set interrupt vectors at 0xFFFF0000

; Extras for some newer versions eg. ARM920 with architecture version 4.
MMU_Control_F  EQU0x400    ; IMPLEMENTATION DEFINED
MMU_Control_Z  EQU0x800    ; Enable branch predicion
MMU_Control_RR EQU0x4000   ; Select non-random cache replacement
   
DOM_CLIENT      EQU0x01   
CTRL_CLKA  EQU  0xC0000000  ; Asynchronous clock select
FAULT_CHECK     EQU     0x2   


Reset_Handler

; --- Initialize stack pointer registers      
; --- Enter each mode in turn and set up the stack pointer
  
        LDR     r0, =top_of_stacks            
        MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
        SUB     sp, r0, #Offset_FIQ_Stack


        MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
        SUB     sp, r0, #Offset_IRQ_Stack
  

        MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
        SUB     sp, r0, #Offset_ABT_Stack


        MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit ; No interrupts
        SUB     sp, r0, #Offset_UND_Stack


        MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
        SUB     sp, r0, #Offset_SVC_Stack
        MSR     CPSR_c, #Mode_SVC:OR:NO_INT         ; disable interrupt

movr0, #0
mcrp15, 0, r0, c7, c10, 4  ; drain WB
mcrp15, 0, r0, c8, c7, 0  ; invalidate I & D TLBs

; --- Invalidate caches (arm920_setup)
MOVr0, #0
MCRp15, 0, r0, c7, c7, 0 ; invalidate I,D caches on v4
MCRp15, 0, r0, c7, c10, 4 ; drain write buffer on v4
MCRp15, 0, r0, c8, c7, 0 ; invalidate I,D TLBs on v4

IMPORT mmutable_level1         ; MMU Level 2 translation table
LDR    r0, =mmutable_level1    ; Load TTB register with MMU table
MCR    p15, 0, r0, c2, c0, 0
;MRC    p15, 0, r1, c2, c0, 0    ; verify the value just writed, no use

; --- set domain access,set domain 0 bit
LDR    r0, =DOM_CLIENT         
MCR    p15, 0, r0, c3, c0, 0
MRC    p15, 0, r1, c3, c0, 0    ; verify the value just writed, no use

MRC   p15, 0, r0, c1, c0, 0    ; Read Control Register, r1 = 0x78
bic r0,r0,  #MMU_Control_I:OR:MMU_Control_X
bic r0,r0,  #MMU_Control_S:OR:MMU_Control_R
bic r0,r0,  #MMU_Control_W:OR:MMU_Control_M:OR:MMU_Control_A:OR:MMU_Control_C
bic r0,r0,  #0xc0000000
;RR    r0, r0, #CTRL_CLKA    ; Set clocking mode
;ORRr0, r0, #FAULT_CHECK  ; .... .... .... ..1.
;ORR    r0, r0, #MMU_Control_M ; enable MMU
   .... .... .... ...1
;MCR  p15, 0, r0, c1, c0, 0   ; Write Control Register
;ORR  r0, r0, #(MMU_Control_C)   ; enable DCache
; .... .... .... .1..
;ORR  r0, r0, #(MMU_Control_I); enable ICache
; ...1 .... .... ....
orrr0,r0,  #MMU_Control_A
;orr r0,r0,  #MMU_Control_C  
orr r0,r0,  #MMU_Control_W  
;orr r0,r0,  #MMU_Control_I
orr r0,r0,  #MMU_Control_M
orr r0,r0,  #0x40000000

mmutable_level1


L1Entry SECTION, (0:SHL:20), ALL_ACCESS, 0, (U_BIT :or: C_BIT :or: B_BIT)
L1Entry SECTION, (1:SHL:20), ALL_ACCESS, 0, (U_BIT :or: C_BIT :or: B_BIT)
L1Entry SECTION, (2:SHL:20), ALL_ACCESS, 0, (U_BIT) ;set stack to non-cached, non-buffered "3"
L1Entry SECTION, (3:SHL:20), ALL_ACCESS, 0, (U_BIT :or: C_BIT :or: B_BIT)
MCR  p15, 0, r0, c1, c0, 0  ; Write Control Register
        
; --- Now enter the C code
MSR     CPSR_c, #Mode_SVC:AND:0x3f ;svc and enable
B       entry1   

MACRO
L1Entry $type, $addr, $acc, $dom, $ucb
[ $type = SECTION
  DCD ( (($addr) :AND: &FFF00000) :OR: \
(($acc) :SHL: 10) :OR: \
(($dom) :SHL: 5) :OR: $ucb :OR: $type )
  MEXIT
]
[ $type = COARSE_PAGE
  DCD ( $addr :OR: \
(($dom) :SHL: 5) :OR: $ucb :OR: $type )
  MEXIT
]
[ $type = FINE_PAGE
  DCD ( (($addr) :AND: &FFFFF000) :OR: \
(($dom) :SHL: 5) :OR: $ucb :OR: $type )
|
  DCD 0 ; Invalid Level 1 Table Entry
]
MEND

以上是arm922t bootloader,现在的问题是，到程序入口处，有压栈操作，但从波形上来看，从寄存里取出的data都是X,不知道是什么问题，压栈之前，对寄存器操作都没有事儿。
那位大虾，能帮忙看一下。这个问题是因为mmu设置有问题还是因为其他。感觉该弄得都弄了。
栈顶是0x0030_0000,压栈时由0x3000000向低地址减。entry1是入口程序。

seewei

顶

冷弦

哪位能帮忙看一下？谢谢了