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TA的资源

一粒金砂(高级)

仿真+简单尝试下TLV62130的几种仿真 [复制链接]

最近做的一个板子的电源部分有问题,估测输出1.8V,实际输出高达11v,仿真来看下是哪里的问题

1.资料查找

所用型号为TLV62130: TLV62130 数据表、产品信息和支持 | 德州仪器 TI.com.cn

  image.png  

TI针对这款芯片有完整的中文手册和数据表:

TLV62130x 采用 3x3 QFN 封装的 3V 至 17V 3A 降压转换器 datasheet (Rev. H) (ti.com.cn)

我们要做的是仿真,看一下是哪里出了问题

当然,最简单的可以直接在下面TI的webbench  直接仿真:

image.png 不过这个只能看下LAYOUT建议和转换效率,以及TI官方给出的原理图。

2.multisim仿真

要是想修改电路和在已有板卡的基础上仿真,还是要用到multisim,笔者自用multisim版本为14.3教育版

TI针对仿真文件给出了多种仿真模型:我们最常用的是第一款SPICE的模型

image.png  

下载好之后,还需要对其进行一定的修改:把 .lib 文件修改为.cir 文件

image.png  

关于导入请看这部分:在没有组件向导的情况下将SPICE模型导入Multisim - NI,写的很详细

直接跳过到后面部分:

image.png    

导入中遇到个小问题:

 
微信图片_20240714103659.jpg
可以按照这篇文章修改:【Multisim】关于导入TI的SPICE模型发生的报错_the model contains multiple-CSDN博客,给文件中添加两处*就可以
另外要注意QFN封装的中间的地也是一个引脚,最好加上,这样是16+1一共17个PIN,否则会出现以下问题:
 

image.png  

成功添加如图:

image.png  

接下来按照电路所画的原理图来仿真就可以了

故障部分原理图如图:

image.png  

简单画一下仿真图:画的不好请多包涵

 

image.png  

可以看到,这个电源的仿真8V实际测量的11v几乎相当,可以确认是电源设计不合理,而且还有地方短路,需要重新修改电路

3.QSPICE仿真:

正好版主推荐了QSPICE这个软件,不妨也来试一下

导入元器件相比multisim更加简单,只需要打开之前下载的文件,将代码复制到剪贴板:

.SUBCKT TLV62130_TRANS PVIN1 PVIN2 AVIN EN
+ SS_TR DEF FSW PGND2 PGND1 ETPAD AGND PG
+ FB VOS SW3 SW2 SW1
R_R11         VIN AVIN  1m  
R_R13         SW3 SW  1m  
V_U3_V5         U3_N11301 0 1.2
I_U3_I1         U3_N11301 U3_N10915 DC 6.4u  
D_U3_U10         U3_N10915 U3_N11301 d_d1
X_U3_U11         DRVL_PRE U3_N12733 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
C_U3_C2         0 U3_N10915  480f  
X_U3_S1    U3_N12733 0 U3_N10915 0 Mintoff_U3_S1 
X_U3_U9         U3_N14024 U3_N10915 MIN_TOFF COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
V_U3_V4         U3_N14024 0 667m
R_R15         SW1 SW  1m  
D_U6_U17         U6_N16592 U6_N17195 d_d1
X_U6_U14         U6_N15145 DRVH_PRE CAPRIO N20512 SRLATCHRHP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U6_U20         U6_N16390 U6_N16592 U6_N26794 PAUSE AND3_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
V_U6_V1         U6_N23722 0 1.5m
C_U6_C4         0 U6_N16592  1n  
X_U6_U19         VIN U6_N25747 U6_N26794 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
X_U6_U18         DRVH_PRE DRVL_PRE U6_N17195 NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U6_U12         U6_N23722 ISENSE_LS U6_N14289 COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
E_U6_ABM1         U6_N26428 0 VALUE { (V(VOS) * 1.15)    }
R_U6_R4         U6_N26428 U6_N25747  1  
R_U6_R3         U6_N17195 U6_N16592  1.44k  
X_U6_U16         MODE_LOGIC U6_N16390 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U6_U13         DRVL_PRE U6_N14289 U6_N15145 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
C_U6_C5         0 U6_N25747  1n  
V_U5_V3         U5_N12138 0  
+PULSE 0 1 1u 10n 10n 1000 2000
E_U5_ABM4         U5_N20257 0 VALUE { IF(V(VOS) < 0.5, 1.2, 3.2)    }
X_U5_U15         U5_N38320 CLIMIT_LS BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
R_U5_R5         U5_N20257 U5_LSLIMIT_THRESH  1  
X_U5_U3         ISENSE_HS U5_HSLIMIT_THRESH U5_N36255 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
R_U5_R10         U5_N478281 U5_HSLIMIT_THRESH  1  
C_U5_C5         0 U5_LSLIMIT_THRESH  1n  
R_U5_R6         U5_N500741 U5_N49148  1  
E_U5_ABM2         U5_N145201 0 VALUE { (V(U5_N06443) + 2.9)    }
C_U5_C10         0 U5_HSLIMIT_THRESH  1n  
X_U5_U1         U5_LSLIMIT_THRESH ISENSE_LS U5_N25875 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
R_U5_R3         U5_N145201 U5_N03743  1  
C_U5_C3         0 U5_N03743  1n  
E_U5_ABM5         U5_N478281 0 VALUE { IF(V(VOS) < 0.5, 1.8,   
+ V(U5_N49148))   }
X_U5_U5         VIN U5_N03743 UVLO_OUT COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
X_U5_U16         PAUSE DRVL_PRE U5_CL_MASK N47303 SRLATCHRHP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U5_U2         DRVL_PRE U5_N25875 U5_N38308 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U5_R2         U5_N06376 U5_N06443  1  
C_U5_C9         0 U5_N38320  1n  
X_U5_U13         U5_N35681 CLIMIT_HS BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
X_U5_U4         U5_N36255 DRVH_PRE U5_N35669 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
C_U5_C8         0 U5_N35681  1n  
R_U5_R9         U5_N38308 U5_N38320  4  
E_U5_ABM6         U5_N500741 0 VALUE { IF(V(U5_CL_MASK) > 0.5, 2.5, 4)    }
C_U5_C2         0 U5_N06443  1n  
R_U5_R8         U5_N35669 U5_N35681  25  
E_U5_ABM1         U5_N06376 0 VALUE { (V(UVLO_OUT) * -200m)    }
D_U5_U14         U5_N38320 U5_N38308 d_d1
X_U5_U9         UVLO_OUT EN_LOGIC U5_N12138 SDWN_N AND3_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
D_U5_U12         U5_N35681 U5_N35669 d_d1
C_U5_C6         0 U5_N49148  1n  
X_U4         MIN_TOFF MIN_TOFF_N INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_R8         0 PGND2  1m  
R_U4_R2         U4_N15867 MODE_LOGIC  1  
E_U4_ABM4         U4_N17314 0 VALUE { IF(V(FSW) > 0.895,1,0)    }
E_U4_ABM2         U4_N15867 0 VALUE { IF(V(MODE) > 0.8,1,0)    }
X_U4_S1    U4_N18546 0 EN 0 LogicTrans_U4_S1 
C_U4_C4         0 FSW_LOGIC  1n  
X_U4_U1         EN_LOGIC U4_N18546 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
E_U4_ABM1         U4_N15535 0 VALUE { IF(V(EN) > 0.895,1,0)    }
X_U4_S3    U4_N19391 0 FSW 0 LogicTrans_U4_S3 
C_U4_C1         0 EN_LOGIC  1n  
X_U4_S2    U4_N19171 0 DEF 0 LogicTrans_U4_S2 
R_U4_R1         U4_N15535 EN_LOGIC  1  
C_U4_C2         0 MODE_LOGIC  1n  
R_U4_R3         U4_N16997 DEF_LOGIC  1  
X_U4_U3         FSW_LOGIC U4_N19391 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
E_U4_ABM3         U4_N16997 0 VALUE { IF(V(DEF) > 0.895,1,0)    }
X_U4_U2         DEF_LOGIC U4_N19171 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
C_U4_C3         0 DEF_LOGIC  1n  
R_U4_R4         U4_N17314 FSW_LOGIC  1  
X_U3         MIN_TON MIN_TON_N INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U9         U2_N14352 U2_N10820 MIN_TON COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
V_U2_V5         U2_N19572 0 1.2
R_U2_R2         SWBY4 U2_N14352  1.3MEG  
C_U2_C2         0 U2_N10820  2.20p  
V_U2_V4         U2_N19580 0 667m
R_U2_R1         U2_N21998 VIN  630k  
I_U2_I1         U2_N19572 U2_N19824 DC 4.7m  
X_U2_U11         DRVH_PRE U2_N12733 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
D_U2_U10         U2_N19824 U2_N19572 d_d1
X_U2_U12         DRVH_PRE U2_N19880 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
C_U2_C4         0 U2_N19824  480p  
X_U2_S3    FSW 0 U2_N21998 U2_N10820 Minton_U2_S3 
X_U2_S2    U2_N19880 0 U2_N19824 0 Minton_U2_S2 
X_U2_S1    U2_N12733 0 U2_N10820 0 Minton_U2_S1 
X_U2_U13         U2_N19580 U2_N19824 MIN_TON_ABS COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
C_U2_C3         0 U2_N14352  5p  
E_GAIN1         N73876 0 VALUE {1 * V(HS_ON)}
R_R12         SW2 SW  1m  
V_V1         MODE 0 0Vdc
X_U8_U27         U8_N123495 U8_N97725 N127397 U8_N129154 SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U8_U9         U8_PWM U8_N96933 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U20         LS_ON U8_LS_ON_N INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U799         U8_N109134 SDWN U8_N96973 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U797         U8_N97687 U8_N97707 SDWN_N U8_LDRV_PBIAS U8_LS_SET
+  AND4_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U8_U23         CLIMIT_HS U8_N97725 CL_DET U8_N129006 SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U8_U29         PWMIN U8_N129006 U8_N129154 U8_PWM AND3_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U8_U22         MIN_TOFF_N U8_PWM U8_N96977 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U800         DRVL_PRE U8_N125193 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=40n
R_U8_R1         U8_N96973 U8_HS_RST  800  
X_U8_U28         U8_N125193 DRVL_PRE U8_N123495 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U8_U798         CAPRIO SDWN U8_N96977 U8_LDRV_PBIASBAR U8_LS_RST
+  OR4_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U8_U26         U8_N96933 MIN_TON_N MIN_TON_ABS_N U8_N109134 AND3_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U8_U14         HS_ON U8_HS_ON_N INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U18         U8_LS_SET U8_LS_RST U8_N97631 U8_LS_ON_PRE
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U8_U17         CAPRIO U8_N97707 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U7         U8_LS_ON_PRE SDWN_N U8_PWM U8_HS_SET AND3_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U8_U795         PWMIN SDWN U8_LDRV_PBIAS U8_LDRV_PBIASBAR
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
C_U8_C1         0 U8_HS_RST  10p  
X_U8_U25         CLIMIT_LS SDWN U8_N97725 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U8         U8_HS_SET U8_HS_RST HS_ON N96925 SRLATCHRHP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
D_U8_U12         U8_N96973 U8_HS_RST d_d1
X_U8_U13         U8_HS_ON_N U8_N96933 U8_N97687 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U8_U15         U8_HS_ON_N U8_N97631 LS_ON AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_R4         0 EN  160MEG  
X_U26         N73924 P100 BUF_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_V2         N184131 0 7.4
X_U7_U11         HS_ON U7_N33760 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=8n
V_U7_V2         SW U7_N37456 320m
X_U7_H2    U7_N33844 0 0 ISENSE_LS Driver_U7_H2 
X_U7_U6         U7_N37456 U7_N33952 d_d1special 
V_U7_V1         U7_N754010 SW 320m
X_U7_H1    PVIN U7_N33952 ISENSE_HS 0 Driver_U7_H1 
X_U7_U4         U7_N33832 U7_N33808 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=6n
X_U7_U2         U7_N33760 U7_N33764 DRVH_PRE AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U7_S3    DRVH_PRE 0 U7_N33952 SW Driver_U7_S3 
X_U7_U3         U7_N33832 U7_N33808 DRVL_PRE AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U7_U12         LS_ON U7_N33832 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=8n
X_U7_U5         U7_N33844 U7_N754010 d_d1special 
X_U7_U1         U7_N33760 U7_N33764 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=6n
X_U7_S4    DRVL_PRE 0 SW U7_N33844 Driver_U7_S4 
R_R7         0 AGND  1m  
E_ABM1         N128939 0 VALUE { IF(V(VIN) > 6V, 6, V(VIN))    }
E_U11_ABM2         U11_N222011 0 VALUE { {(LIMIT(V(SS_TR), 0, 1.25)  
+ )*0.64}   }
V_U11_V1         U11_N221204 0 4.8
R_U11_R10         U11_N222011 U11_N222353  1  
C_U11_C5         0 U11_N222353  1n  
E_U11_ABM4         U11_N231653 0 VALUE { (1+ (V(DEF_LOGIC) *50m) +   
+ (V(P100)*5m))*  
+ V(U11_N222353)  }
R_U11_R9         U11_N220353 U11_N220347  1  
X_U11_S1    U11_N226363 0 SS_TR 0 SoftStart_U11_S1 
E_U11_ABM1         U11_N220347 0 VALUE { IF(V(SDWN_N) < 0.5,0,1)    }
X_U11_U9         SDWN_N U11_N226363 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
C_U11_C4         0 U11_N220353  1n  
R_U11_R11         U11_N231653 INT_VREF  1  
D_U11_U8         SS_TR U11_N221204 d_d1 
C_U11_C6         0 INT_VREF  1n  
G_U11_ABMII1         U11_N221204 SS_TR VALUE { V(U11_N220353)*2.5u    }
C_U11_C7         0 SS_TR  5p  
X_U6         SDWN_N SDWN INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_C3         0 VIN_LDO  1n  
R_R9         0 PGND1  1m  
R_R10         PVIN PVIN2  1m  
E_U1_ABM4         U1_N273241 0 VALUE { LIMIT(((V(INT_VREF) -V(FB))*5.3u),  
+ 500n,-500n)   }
R_U1_R3         U1_N147079 SW  667k  
R_U1_R7         0 U1_N147163  6.67k  
R_U1_R11         U1_INNER_REF 0  2.4G  
X_U1_U2         U1_INNER_REF U1_INNER_FB U1_N264687 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U1_U3         FB U1_N147219 U1_N147271 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
E_U1_ABM10         U1_INNER_REF_CLAMP 0 VALUE { MIN(V(VIN),5)    }
X_U1_U8         PAUSE P100 U1_FBREF_SHORT OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
G_U1_ABMII2         U1_N147365 U1_N147247 VALUE { V(U1_VCTRLM)    }
C_U1_C10         0 U1_VCTRLM  1n  
X_U1_S3    SDWN_N 0 U1_INNER_FB U1_INNER_REF ErrorAmp_U1_S3 
V_U1_V6         U1_N194447 0 0.744
X_U1_U11         U1_N264687 U1_N265822 PAUSE PWMIN MUX2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
R_U1_R20         0 U1_N265822  50  
R_U1_R15         U1_N148765 U1_N195543  1  
V_U1_V2         U1_N147219 0 0.76
X_U1_U10         FB U1_N194447 U1_N194443 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
T_U1_T1         U1_N264687 0 U1_N265822 0 Z0=50 TD=300n  
R_U1_R12         U1_N147133 U1_N148771  1  
R_U1_R6         U1_INNER_REF U1_ISINK  750k  
G_U1_ABM3I1         0 U1_INNER_REF VALUE { IF((V(SDWN_N) < 0.5) |  
+ (V(CL_DET) > 0.5),0,  
+ V(U1_N148405))  }
D_U1_U6         U1_INNER_REF U1_INNER_REF_CLAMP d_d1 
C_U1_C9         0 U1_N148765  1n  
V_U1_V1         U1_N147365 0 15m
R_U1_R8         SWBY4 U1_N147079  844.4k  
C_U1_C1         VOS U1_INNER_FB  20p  
X_U1_U5         SDWN_N U1_N147377 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
D_U1_U1         U1_N147247 U1_N147365 d_d1
R_U1_R19         U1_N180936 U1_VCTRLM  1  
X_U1_U4         U1_N147271 U1_N147377 N148783 U1_SOFTSTART SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
R_U1_R17         0 SWBY4  500k  
E_U1_ABM8         U1_N195543 0 VALUE { IF(V(U1_N194443) > 0.5,V(U1_VCLAMP),  
+ 125n)   }
X_U1_S1    U1_FBREF_SHORT 0 U1_INNER_FB U1_ISINK ErrorAmp_U1_S1 
R_U1_R1         U1_INNER_FB U1_N147079  1.337MEG  
C_U1_C6         0 U1_N148771  1n  
R_U1_R13         U1_VCLAMP U1_N273241  1  
C_U1_C3         U1_N147163 U1_INNER_REF  10p  
G_U1_ABMII3         U1_ISINK 0 VALUE { IF(V(CL_DET) > 0.5,125n,0)    }
D_U1_U9         0 U1_INNER_REF d_d1
X_U1_S2    HS_ON 0 U1_N147247 U1_N147163 ErrorAmp_U1_S2 
X_U1_U7         U1_N148765 U1_N148771 U1_SOFTSTART U1_N148405 MUX2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
C_U1_C7         0 U1_VCLAMP  1n  
E_U1_ABM6         U1_N180936 0 VALUE { IF(V(HS_ON) > 0.5,1.5u,0)    }
E_U1_ABM3         U1_N147133 0 VALUE { IF(V(U1_VCLAMP) > 125n, 125n,  
+ IF (V(U1_VCLAMP) <-125n,  
+ -125n,V(U1_VCLAMP)))  }
D_U20         VOS N184131 d_d1
C_C4         FB VOS  25p  
X_U9         MIN_TON_ABS MIN_TON_ABS_N INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_R5         N128939 VIN_LDO  1  
R_R16         0 ETPAD  1m  
R_R3         N73876 N73924  200k  
R_R14         PVIN PVIN1  1m  
C_C2         0 N73924  1n  
R_U10_R3         U10_N222172 U10_N14135  1  
R_U10_R1         U10_N14627 U10_N00497  14.4k  
E_U10_ABM6         U10_N2217831 0 VALUE { (V(INT_VREF)*-0.05*  
+ +V(U10_OUT2))   }
X_U10_U5         FB U10_N14135 U10_N14627 COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
E_U10_ABM7         U10_N222172 0 VALUE { (V(U10_N221839)+  
+ +V(U10_N222445))   }
R_U10_R6         U10_N2217831 U10_N221839  1  
C_U10_C6         0 U10_N221839  1n  
X_U10_U6         U10_N00497 U10_N21024 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U10_R4         U10_N2192031 U10_N222445  1  
D_U10_U7         U10_N00497 U10_N14627 d_d1
C_U10_C3         0 U10_N14135  1n  
E_U10_ABM4         U10_N2192031 0 VALUE { MAX(V(INT_VREF)*0.95,0.76)    }
C_U10_C4         0 U10_N222445  1n  
X_U10_S1    U10_N22863 0 PG 0 PG_SGND_U10_S1 
X_U10_U9         U10_N00497 U10_OUT2 BUF_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
C_U10_C1         0 U10_N00497  1n  
X_U10_U8         U10_N21024 EN_LOGIC UVLO_OUT U10_N22863 AND3_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
D_U19         N73924 N73876 d_d1
.ENDS TLV62130_TRANS
*$
.subckt Mintoff_U3_S1 1 2 3 4  
S_U3_S1         3 4 1 2 _U3_S1
RS_U3_S1         1 2 1G
.MODEL         _U3_S1 VSWITCH Roff=10e6 Ron=1.0 Voff=0.2 Von=0.8
.ends Mintoff_U3_S1
*$
.subckt LogicTrans_U4_S1 1 2 3 4  
S_U4_S1         3 4 1 2 _U4_S1
RS_U4_S1         1 2 1G
.MODEL         _U4_S1 VSWITCH Roff=100e6 Ron=400k Voff=0.2 Von=0.8
.ends LogicTrans_U4_S1
*$
.subckt LogicTrans_U4_S3 1 2 3 4  
S_U4_S3         3 4 1 2 _U4_S3
RS_U4_S3         1 2 1G
.MODEL         _U4_S3 VSWITCH Roff=100e6 Ron=400k Voff=0.2 Von=0.8
.ends LogicTrans_U4_S3
*$
.subckt LogicTrans_U4_S2 1 2 3 4  
S_U4_S2         3 4 1 2 _U4_S2
RS_U4_S2         1 2 1G
.MODEL         _U4_S2 VSWITCH Roff=100e6 Ron=400k Voff=0.2 Von=0.8
.ends LogicTrans_U4_S2
*$
.subckt Minton_U2_S3 1 2 3 4  
S_U2_S3         3 4 1 2 _U2_S3
RS_U2_S3         1 2 1G
.MODEL         _U2_S3 VSWITCH Roff=1 Ron=630k Voff=0.2 Von=0.8
.ends Minton_U2_S3
*$
.subckt Minton_U2_S2 1 2 3 4  
S_U2_S2         3 4 1 2 _U2_S2
RS_U2_S2         1 2 1G
.MODEL         _U2_S2 VSWITCH Roff=10e6 Ron=1.0 Voff=0.2 Von=0.8
.ends Minton_U2_S2
*$
.subckt Minton_U2_S1 1 2 3 4  
S_U2_S1         3 4 1 2 _U2_S1
RS_U2_S1         1 2 1G
.MODEL         _U2_S1 VSWITCH Roff=100e6 Ron=1 Voff=0.2 Von=0.8
.ends Minton_U2_S1
*$
.subckt Driver_U7_H2 1 2 3 4  
H_U7_H2         3 4 VH_U7_H2 1
VH_U7_H2         1 2 0V
.ends Driver_U7_H2
*$
.subckt Driver_U7_H1 1 2 3 4  
H_U7_H1         3 4 VH_U7_H1 1
VH_U7_H1         1 2 0V
.ends Driver_U7_H1
*$
.subckt Driver_U7_S3 1 2 3 4  
S_U7_S3         3 4 1 2 _U7_S3
RS_U7_S3         1 2 1G
.MODEL         _U7_S3 VSWITCH Roff=10e6 Ron=115m Voff=0.2 Von=0.8
.ends Driver_U7_S3
*$
.subckt Driver_U7_S4 1 2 3 4  
S_U7_S4         3 4 1 2 _U7_S4
RS_U7_S4         1 2 1G
.MODEL         _U7_S4 VSWITCH Roff=10e6 Ron=52m Voff=0.2 Von=0.8
.ends Driver_U7_S4
*$
.subckt SoftStart_U11_S1 1 2 3 4  
S_U11_S1         3 4 1 2 _U11_S1
RS_U11_S1         1 2 1G
.MODEL         _U11_S1 VSWITCH Roff=1e9 Ron=100 Voff=0.2 Von=0.8
.ends SoftStart_U11_S1
*$
.subckt ErrorAmp_U1_S3 1 2 3 4  
S_U1_S3         3 4 1 2 _U1_S3
RS_U1_S3         1 2 1G
.MODEL         _U1_S3 VSWITCH Roff=1 Ron=10G Voff=0.2V Von=0.9V
.ends ErrorAmp_U1_S3
*$
.subckt ErrorAmp_U1_S1 1 2 3 4  
S_U1_S1         3 4 1 2 _U1_S1
RS_U1_S1         1 2 1G
.MODEL         _U1_S1 VSWITCH Roff=1000e6 Ron=1 Voff=0.4V Von=0.8V
.ends ErrorAmp_U1_S1
*$
.subckt ErrorAmp_U1_S2 1 2 3 4  
S_U1_S2         3 4 1 2 _U1_S2
RS_U1_S2         1 2 1G
.MODEL         _U1_S2 VSWITCH Roff=100e6 Ron=1m Voff=0.4V Von=0.8V
.ends ErrorAmp_U1_S2
*$
.subckt PG_SGND_U10_S1 1 2 3 4  
S_U10_S1         3 4 1 2 _U10_S1
RS_U10_S1         1 2 1G
.MODEL         _U10_S1 VSWITCH Roff=30e6 Ron=150 Voff=0.2V Von=0.8
.ends PG_SGND_U10_S1
*$
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND2_BASIC_GEN
*$
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND3_BASIC_GEN
*$
.SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH} &
+ V(D) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND4_BASIC_GEN
*$
.SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND2_BASIC_GEN
*$
.SUBCKT NAND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND3_BASIC_GEN
*$
.SUBCKT NAND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH} &
+ V(D) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND4_BASIC_GEN
*$
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR2_BASIC_GEN
*$
.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR3_BASIC_GEN
*$
.SUBCKT OR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR4_BASIC_GEN
*$
.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR2_BASIC_GEN
*$
.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR3_BASIC_GEN
*$
.SUBCKT NOR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR4_BASIC_GEN
*$
.SUBCKT NOR5_BASIC_GEN A B C D E Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH} |
+ V(E) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR5_BASIC_GEN
*$
.SUBCKT NOR6_BASIC_GEN A B C D E F Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH} |
+ V(E) > {VTHRESH} |
+ V(F) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR6_BASIC_GEN
*$
.SUBCKT INV_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS INV_BASIC_GEN
*$
.SUBCKT XOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE  YINT 0 VALUE {{IF(V(A) > {VTHRESH}  ^  
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS XOR2_BASIC_GEN
*$
.SUBCKT XNOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE  YINT 0 VALUE {{IF(V(A) > {VTHRESH}  ^  
+ V(B) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS XNOR2_BASIC_GEN
*$
.SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE  YINT 0 VALUE {{IF(V(S) > {VTHRESH},  
+ V(B),V(A))}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS MUX2_BASIC_GEN
*$
.SUBCKT INV_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n 
E_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , 
+ {VSS},{VDD})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS INV_DELAY_BASIC_GEN
*$
.SUBCKT BUF_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n 
E_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS BUF_DELAY_BASIC_GEN
*$
.SUBCKT BUF_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS BUF_BASIC_GEN
*$
**Set has higher priority in this latch
.SUBCKT SRLATCHSHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R)>{VTHRESH},-5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1 
Cdummy1 Q 0 1n 
Cdummy2 QB 0 1n 
.IC V(Qint) {VSS}
.ENDS SRLATCHSHP_BASIC_GEN
*$
**Reset has higher priority in this latch
.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1 
Cdummy1 Q 0 1n 
Cdummy2 QB 0 1n
.IC V(Qint) {VSS}
.ENDS SRLATCHRHP_BASIC_GEN
*$
**Reset has higher priority in this latch and active low set and reset - basically NAND based SR latch
.SUBCKT SBRBLATCHRHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB) < {VTHRESH},5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1 
.IC V(Qint) {VSS}
.ENDS SBRBLATCHRHP_BASIC_GEN
*$
**Reset has higher priority in this latch and active low set and reset - basically NAND based SR latch
.SUBCKT SBRBLATCHSHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
GQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB) < {VTHRESH},-5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1 
.IC V(Qint) {VSS}
.ENDS SBRBLATCHSHP_BASIC_GEN
*$
.SUBCKT DFFSBRB_SHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
***Set has higher priority in this
** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations
**Faster flip-flops require a a smaller time step to simulate
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB)<{VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, 
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1 
Cdummy1 Q 0 1nF 
Cdummy2 QB 0 1nF 
.IC V(Qint) {VSS}
.ENDS DFFSBRB_SHPBASIC_GEN
*$
.SUBCKT DFFSR_SHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
***Set has higher priority in this
** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations
**Faster flip-flops require a a smaller time step to simulate
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} 
GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R) > {VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, 
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1 
Cdummy1 Q 0 1nF 
Cdummy2 QB 0 1nF 
.IC V(Qint) {VSS}
.ENDS DFFSR_SHPBASIC_GEN
*$
.SUBCKT DFFSBRB_RHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
***Set has higher priority in this
** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations
**Faster flip-flops require a a smaller time step to simulate
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} 
GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB)< {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, 
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 5
D_D11 0 Qint D_D1 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1 
Cdummy1 Q 0 1nF 
Cdummy2 QB 0 1nF 
.IC V(Qint) {VSS}
.ENDS DFFSBRB_RHPBASIC_GEN
*$
.SUBCKT DFFSR_RHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
***Set has higher priority in this
** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations
**Faster flip-flops require a a smaller time step to simulate
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}  
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S) > {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, 
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1 
Cdummy1 Q 0 1nF 
Cdummy2 QB 0 1nF 
.IC V(Qint) {VSS}
.ENDS DFFSR_RHPBASIC_GEN
*$
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5	
E_ABM Yint 0 VALUE {IF (V(INP) > 
+ V(INM), {VDD},{VSS})}
R1 Yint Y 1
C1 Y 0 1n
.ENDS COMP_BASIC_GEN
*$
.subckt d_d 1 2
d1 1 2 dd
.model dd d
+ is=1e-015
+ n=0.01
+ tt=1e-011
.ends d_d
*$
.MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.05 N=.1  )
*$
.SUBCKT D_D1special 1 2
D1 1 2 DD1spec
.MODEL DD1spec D( IS=1e-15 TT=10p Rs=0.8 N=.1  )
.ENDS D_D1special
*$
.SUBCKT LDCR 1 2 PARAMS: L=1u DCR=20m
L1 1 INT1 {L}
R1 INT1 2 {DCR}
.ENDS LDCR
*$
.SUBCKT CESR 1 2 PARAMS: C=10u ESR=2m ESL=1n
C1 1 INT1 {C}
R1 INT1 INT2 {ESR}
L1 INT2 2 {ESL}
.ENDS CESR
*$

 

之后直接在界面中粘贴:(记得勾选INCLUDE)

image.png

点YES即可导入元器件:

image.png   

搭建电路:

image.png   在页面中直接粘贴命令:

.tran 500m
.plot V(out)
.plot V(vcc)

 之后运行,就能看到完整的仿真图和纹波了:

370c39c3ba58b78cc44255880344d31.png  

可以看到,不仅设计电压有偏差,电源纹波也很大,需要修正一下硬件部分

参考文档:QSPICE电子电路仿真器 - 电力电子新闻 (powerelectronicsnews.com)

QSPICE™ 快速入门 - Qorvo

最新回复

gtq
哇呜~~酷~~~赞赞赞~~等到啦这可真不容易   详情 回复 发表于 2024-7-17 16:35
个人签名

没用比没有强


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五彩晶圆(高级)

QSPICE仿真相比multisim更加简单,这个个不错

谢谢楼主分享


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一粒金砂(中级)

 为啥不用 kicad,日常画图和 spice 仿真一站式解决。

点评

KICAD只用过它画过图,没用过仿真。 请问有教程指路吗,感谢大佬  详情 回复 发表于 2024-7-15 20:27

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管理员

谢谢楼主分享!~很详细~~

还来了个对比

加EE小助手好友,
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个人签名

玩板看这里:

https://bbs.eeworld.com.cn/elecplay.html

EEWorld测评频道众多好板等你来玩,还可以来频道许愿树许愿说说你想要玩的板子,我们都在努力为大家实现!


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一粒金砂(初级)

仿真图错了,240k应该连在FB跟GND之间,你连到SW脚了


点评

[attachimg]824333[/attachimg]   感谢大佬指正,不过问题貌似依然没有解决,电压还是远高于设计VOUT  详情 回复 发表于 2024-7-15 20:25

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一粒金砂(高级)

忠耿 发表于 2024-7-15 17:41 仿真图错了,240k应该连在FB跟GND之间,你连到SW脚了

image.png    感谢大佬指正,不过问题貌似依然没有解决,电压还是远高于设计VOUT

个人签名

没用比没有强


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113

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一粒金砂(高级)

dukedz 发表于 2024-7-15 11:00  为啥不用 kicad,日常画图和 spice 仿真一站式解决。

KICAD只用过它画过图,没用过仿真。

请问有教程指路吗,感谢大佬

个人签名

没用比没有强


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一粒金砂(中级)

谢谢楼主分享!~很详细~~

还来了个对比


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一粒金砂(初级)

电子烂人 发表于 2024-7-15 20:25    感谢大佬指正,不过问题貌似依然没有解决,电压还是远高于设计VOUT

输入12V没有接地


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一粒金砂(中级)

如果做TI器件的仿真,可以去TI下载PSPICE for TI,也是免费的。库里面TI的元件很齐全,新的开关电源芯片也都有, 还会定期在线更新元件库。因为TI做过大部分模拟器件,所以很多经典的二三极管,运放什么的都不需要另外导入。PSPICE除了速度慢点,没什么大毛病。另外得下载23版的,24版的库有点问题,安装后没有任何器件。


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一粒金砂(中级)

哇呜~~酷~~~赞赞赞~~等到啦这可真不容易


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