求救，verilog初学者问题，急急急

holly8301

求救，verilog初学者问题，急急急 [复制链接]

写了一个四选一数据选择器，结果在quatus中一编译就出现这样的错误，不知道为什么，请前辈们帮们分析一下，关系到我学习它的信心啊，帮忙！！！

Error (10170): Verilog HDL syntax error at gete4_1.v(5) near text "case"; expecting an identifier ("case" is a reserved keyword ), or "endmodule", or a parallel statement

Error (10112): Ignored design unit "gate4_1" at gete4_1.v(1) due to previous errors

源程序：
module gate4_1 (a,b,c,d,sel,f);
input a,b,c,d;
input [1:0]sel;
output f;
case(sel)
0:f=a;
1:f=b;
2:f=c;
3:f=d;
endcase
endmodule

woshiguizi

"case" can only be used in "always" procedure.a

Your code should looks like:

reg f;
always@(a or b or c or d or sel)
begin
  case(sel)
  2'b00: f <= a;
  2'b01: f <= b;
  2'b10: f <= c;
  2'b11: f <= d;
  endcase
end
endmodule