统计数据中1的个数的问题

chenbingjy

统计数据中1的个数的问题 [复制链接]

 

verilog程序

module ones(clk,rst,count_1);
input clk;
input rst;
inout reg [3:0]  count_1;
reg [3:0] j;
reg [3:0] i;
reg [3:0] k;




endmodule

test bench程序

`timescale 1 ns/ 1 ps
module ones_vlg_tst();
// constants                                           
// general purpose registers
//reg eachvec;
// test vector input registers
reg clk;
reg [3:0] treg_count_1;
reg rst;
// wires                                               
wire [3:0]  count_1;
reg [3:0] j;
reg [3:0] i;
reg [3:0] k;
reg [3:0] count;
// assign statements (if any)                          
assign count_1 = treg_count_1;
ones i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.count_1(count_1),
	.rst(rst)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
                                                       
// --> end                                             
$display("Running testbench");                       
end                                                    
initial                                               
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
clk=0;
forever
#10 clk=~clk;                                                       
                                           
// --> end                                             
end   
initial                                               
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
begin                                                  
// code executes for every event on sensitivity list   
// insert code here --> begin                          
rst=1;
#15 rst=0;
#15 rst=1;
#1000 $stop;                             
// --> end                                             
end  
always @(posedge clk or negedge rst)   
begin
if(!rst)
	begin
		i<=4'd0;
		count<=4'd0;
		treg_count_1<=4'd0;
	
	end
else
	begin
		treg_count_1<=4'd0;
		for(j=0;j<=3;j=j+1)
			begin
				k<=i;
				if((k&4'b0001)==4'b0001)
					begin
						treg_count_1<=treg_count_1+1;
						
					
					end
				if((k&4'b0010)==4'b0010)
					begin
						treg_count_1<=treg_count_1+1;
						
					
					end
				if((k&4'b0100)==4'b0100)
					begin
						treg_count_1<=treg_count_1+1;
						
					
					end
				if((k&4'b1000)==4'b1000)
					begin
						treg_count_1<=treg_count_1+1;
						
					
					end
				end
		count<=treg_count_1;
		i<=(i+1);
		$display("%d,%d\n",treg_count_1,count);
		//treg_count_1<=4'd0;
		//count<=4'd0;
	end
end                                               
endmodule

运行结果：

明显不对。请问高手，哪里出错了？谢谢

Jacktang

代码是自己写的？

没个注释自己最了解了