LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY light IS
PORT
(
clk,reset,sensor : IN STD_LOGIC;
green_1,green_2,red_1,red_2,yellow_1,yellow_2 : OUT STD_LOGIC
);
END ENTITY light;
ARCHITECTURE a OF light IS
TYPE state IS (s0,s1,s2);
SIGNAL current_state:state;
SIGNAL next_state:state;
SIGNAL c0,c1,c2:STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL from:state;
BEGIN
currents:PROCESS (current_state)
BEGIN
IF reset='1' THEN
next_state<=s0;
ELSE
CASE current_state IS
WHEN s0 =>
green_1<='1';green_2<='0';red_1<='0';red_2<='1';yellow_1<='0';yellow_2<='0';
IF c0="11" AND sensor='1' THEN
next_state<=s1;
from<=s0; -----------------------------------------------------
ELSE next_state<=s0;
END IF;
WHEN s1 =>
green_1<='0';green_2<='0';red_1<='0';red_2<='0';yellow_1<='1';yellow_2<='1';
IF c1="01" THEN
IF sensor='1' AND from=s0 THEN
next_state<=s2;
ELSE next_state<=s0;
END IF;
ELSE next_state<=s1;
END IF;
WHEN s2 =>
green_1<='0';green_2<='1';red_1<='1';red_2<='0';yellow_1<='0';yellow_2<='0';
IF c2="11" THEN
next_state<=s1;
from<=s2;
ELSE next_state<=s2;
END IF;
END CASE;
END IF;
END PROCESS currents;
PROCESS (clk)
BEGIN
IF clk'event AND clk='1' THEN
current_state<=next_state;
END IF;
END PROCESS;
count:PROCESS (clk)
BEGIN
IF clk'event AND clk='1' THEN
IF reset='1' THEN
c0<="00";
c1<="00";
c2<="00";
ELSE
CASE current_state IS
WHEN s0 =>
c0<=c0+1;
WHEN s1 =>
IF c1="01" THEN
c1<="00";
ELSE c1<=c1+1;
END IF;
WHEN s2 =>
c2<=c2+1;
END CASE;
END IF;
END IF;
END PROCESS count;