【国产FPGA 正点原子DFPGL22G开发板】六、上位机通信代码编写

Jimmy_Arareb

【国产FPGA 正点原子DFPGL22G开发板】六、上位机通信代码编写 [复制链接]

<i class="pstatus"> 本帖最后由 Jimmy_Arareb 于 2023-2-25 13:23 编辑 </i>

# 六、 上位机通信代码编写

## 1.SPI接口代码

RDC解算出当前角位置及角速度后，需要通过指定接口传输给上位机，用于后续外环的运动控制等功能。

一般的伺服电机应用中，位置传感器的更新频率与电流环调制频率同步，最高20KHz，按照角位置及角速度均为32位计算，最小带宽约为1.28Mbps。采用相对简易的SPI接口即可满足通信需求。

SPI接口的具体实现思路为：将需要读取的数据映射到对应的寄存器地址，角位置及角速度分为16位一组共4个地址，由于SPI时钟频率相比FPGA内部时钟频率较低，可以将使能、输入时钟及数据信号同步采样至内部时钟域后，利用状态机控制读写时序及完成串并转换。

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> SPI时序图，截取自TMS320F2837xDDual-Core Microcontrollers Technical Reference Manual

采用图中Falling edge without delay选项对应的时序，具体代码如下：

```verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/02/24 21:34:54
// Design Name: 
// Module Name: spi
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module spi (
  input clk,
  input rst,

inputsimo,
  output somi,
  inputsck,
  inputcs,

input [31:0] data1,
  input [31:0] data2
);

localparam idle = 8'b1;
  localparam cs_down = 8'b10;
  localparam trans_start = 8'b100;
  localparam trans_finish = 8'b1000;

localparam addr_data1_31_16 = 16'd0;
  localparam addr_data1_15_0 = 16'd1;
  localparam addr_data2_31_16 = 16'd2;
  localparam addr_data2_15_0 = 16'd3;

reg [ 7:0] state = idle;
  reg [ 7:0] next_state;

reg [15:0] addr = addr_data1_31_16;
  reg [15:0] addr_buf = addr_data1_31_16;

reg [15:0] data1_31_16 = 16'b0;
  reg [15:0] data1_15_0 = 16'b0;
  reg [15:0] data2_31_16 = 16'b0;
  reg [15:0] data2_15_0 = 16'b0;
  reg [15:0] data_buf = 16'b0;

reg [ 4:0] bit_cnt = 5'b0;
  reg [12:0] watchdog_cnt = 13'b0;

reg [ 1:0] sck_buf = 2'b0;
  reg  sck_down_flag = 1'b0;
  reg  sck_up_flag = 1'b0;

assign somi = data_buf[15];

always @(rst, state) begin
  if (~rst) begin
    next_state = cs_down;
  end else begin
    case (state)
      idle: next_state = cs_down;
      cs_down: next_state = trans_start;
      trans_start: next_state = trans_finish;
      trans_finish: next_state = idle;
      default: begin
      next_state = idle;
      end
    endcase
  end
  end

always @(posedge clk) begin
  if (~rst) begin
    state <= idle;
  end else begin
    case (state)
      idle: begin
      if (~cs) begin
        state <= next_state;
      end else begin
        state <= state;
      end
      {data1_31_16, data1_15_0} <= data1;
      {data2_31_16, data2_15_0} <= data2;
      addr        <= addr_buf;
      end
      cs_down: begin
      if (~sck) begin
        state <= next_state;
      end else begin
        state <= state;
      end
      case (addr)
        addr_data1_31_16: data_buf <= data1_31_16;
        addr_data1_15_0: data_buf <= data1_15_0;
        addr_data2_31_16: data_buf <= data2_31_16;
        addr_data2_15_0: data_buf <= data2_15_0;
        default: data_buf <= 16'b0;
      endcase
      end
      trans_start: begin
      if (bit_cnt == 5'h10) begin
        state <= next_state;
      end else begin
        state <= state;
      end
      if (sck_up_flag) begin
        addr_buf <= {addr_buf[14:0], simo};
      end
      if (sck_down_flag) begin
        data_buf <= data_buf << 1'b1;
      end
      end
      trans_finish: begin
      if (cs) begin
        state <= next_state;
      end else state <= state;
      end
      default: begin
      state <= idle;
      end
    endcase
    if (watchdog_cnt == 13'h1fff) begin
      state  <= idle;
      data_buf <= 16'b0;
      addr_buf <= 16'b0;
    end
  end
  end

always @(posedge clk) begin
  if (~rst) begin
    bit_cnt <= 5'b0;
  end else begin
    if (state == trans_start) begin
      if (sck_buf == 2'b01) begin
      sck_up_flag <= 1'b1;
      end else begin
      sck_up_flag <= 1'b0;
      end
      if (sck_buf == 2'b10) begin
      sck_down_flag <= 1'b1;
      bit_cnt   <= bit_cnt + 1'b1;
      end else begin
      sck_down_flag <= 1'b0;
      bit_cnt   <= bit_cnt;
      end
    end else begin
      bit_cnt <= 5'b0;
    end
  end
  end

always @(posedge clk) begin
  if (~rst) begin
    sck_buf <= 2'b0;
  end else begin
    sck_buf <= {sck_buf[0], sck};
    if (watchdog_cnt == 13'h1fff) begin
      sck_buf <= {sck_buf[0], sck};
    end
  end
  end

always @(posedge clk) begin
  if (~rst) begin
    watchdog_cnt <= 0;
  end else begin
    if (state == idle) watchdog_cnt <= 0;
    else watchdog_cnt <= watchdog_cnt + 1'b1;
  end
  end

endmodule
```

考虑到可能出现的传输错误及上位机上电时gpio初始化的问题，在模块内部增加了看门狗计时器，在空闲以外的状态超时后对模块进行复位，防止状态机卡死。

## 1.SPI接口仿真

编写测试激励模拟通信时序，输出结果正确。

```verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/02/25 08:26:05
// Design Name: 
// Module Name: ad_pll_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module ad_pll_tb ();

localparam N = 2000;

localparam addr_data1_31_16 = 1;
  localparam addr_data1_15_0 = 2;
  localparam addr_data2_31_16 = 3;
  localparam addr_data2_15_0 = 0;

reg clk = 0, rst = 0, ad_busy = 0, capture_flag = 0;
  reg [15:0] data_sin  [N - 1:0];
  reg [15:0] data_cos  [N - 1:0];
  reg [15:0] data_in = 0;
  reg [ 1:0] cnt = 0;

wire ad_rd, ad_convstab;
  wire pwm_p, pwm_n;

reg    clk_10k = 0;

reg    simo = 0;
  wire   somi;
  reg    sck = 0;
  reg    cs = 1;

reg [15:0] data_buf = 0;
  reg [15:0] data1_1 = 0;
  reg [15:0] data1_2 = 0;
  reg [15:0] data2_1 = 0;
  reg [15:0] data2_2 = 0;

integer  i = 0;

initial begin
  $readmemh("../../../../matlab/sin.txt", data_sin);
  $readmemh("../../../../matlab/cos.txt", data_cos);
  #50 rst <= 1;
  #20000000 $stop;
  end

always begin
  #10 clk <= ~clk;
  end

always begin
  #50000 clk_10k = ~clk_10k;
  end

always @(posedge ad_convstab) begin
  #40 ad_busy = 1;
  #2000 ad_busy = 0;
  end

always @(negedge ad_rd) begin
  case (cnt)
    3'd0: data_in <= 0;
    3'd1: data_in <= data_sin<i>;
    3'd2: data_in <= 0;
    3'd3: begin
      data_in <= data_cos<i>;
      if (i == N - 1) begin
      i <= 0;
      end else i <= i + 1;
    end
  endcase
  cnt <= cnt + 1;
  end

integer j = 0;
  always @(posedge clk_10k) begin
  #50 cs <= 0;
  sck <= 0;
  for (j = 0; j < 16; j = j + 1) begin
    simo <= addr_data1_31_16[15-j];
    #100 sck <= 1;
    data_buf <= {data_buf[14:0], somi};
    #100 sck <= 0;
  end
  data1_1 <= data_buf;
  cs  <= 1;
  #400 cs <= 0;
  sck <= 0;
  for (j = 0; j < 16; j = j + 1) begin
    simo <= addr_data1_15_0[15-j];
    #100 sck <= 1;
    data_buf <= {data_buf[14:0], somi};
    #100 sck <= 0;
  end
  data1_2 <= data_buf;
  cs  <= 1;
  #400 cs <= 0;
  sck <= 0;
  for (j = 0; j < 16; j = j + 1) begin
    simo <= addr_data2_31_16[15-j];
    #100 sck <= 1;
    data_buf <= {data_buf[14:0], somi};
    #100 sck <= 0;
  end
  data2_1 <= data_buf;
  cs  <= 1;
  #400 cs <= 0;
  sck <= 0;
  for (j = 0; j < 16; j = j + 1) begin
    simo <= addr_data2_15_0[15-j];
    #100 sck <= 1;
    data_buf <= {data_buf[14:0], somi};
    #100 sck <= 0;
  end
  data2_2 <= data_buf;
  cs  <= 1;
  simo  <= 0;

end

top u_top (
  .clk  (clk),
  .rst  (rst),
  .data_in  (data_in),
  .ad_busy  (ad_busy),
  .ad_rd  (ad_rd),
  .ad_convstab(ad_convstab),
  .simo(simo),
  .somi(somi),
  .sck(sck),
  .cs(cs),
  .pwm_p(pwm_p),
  .pwm_n(pwm_n)
  );

endmodule
```

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> Modelsim仿真结果

高进

火辣西米秀

想知道代码实际验证的结果如何

角位置及角速度是否能控制住

Jimmy_Arareb

火辣西米秀发表于 2023-2-26 08:48 想知道代码实际验证的结果如何角位置及角速度是否能控制住

之前用xilinx的片子验证过，没啥问题。后续可能需要再加一些故障检测相关的功能，完善一下配置，但是基本功能是没问题的。

【国产FPGA 正点原子DFPGL22G开发板】六、上位机通信代码编写 [复制链接]

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