【国产FPGA 正点原子DFPGL22G开发板】三、 AD7606驱动编写

Jimmy_Arareb

【国产FPGA 正点原子DFPGL22G开发板】三、 AD7606驱动编写 [复制链接]

# 三、 AD7606驱动编写

[TOC]

## 1. AD7606驱动程序

AD7606是ADI公司出品的一款4/6/8通道同步采样，200kSPS，16位，$\pm$5、$\pm$15V双极性输入的ADC芯片。

### 芯片时序

参考数据手册，采用读取后转换，并口模式。芯片时序如下：

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注意上电后需要先拉高`RESET`对芯片进行复位，否则芯片会工作异常。

开始转换时拉低`CONVST A/B`引脚，等待`BUSY`拉低后转换完成。注意从开始转换到`BUSY`拉高之间的间隔最大为45ns，需要单独设置状态进行处理，否则可能出现误触发。

转换完成后先拉低`CS`再输入时钟`RD`，完成读取后再拉高`CS`，一个采样周期完成。注意数据在`RD`下降沿更新，上升沿读取。

### 程序编写

采用状态机控制读取，上电及复位时进入`RESET`状态，先对AD7606进行复位。

复位完成后进入`IDLE`状态，等待数据采集开始标志输入。

开始采集后进入`WAIT_1`状态，完成计时后进入`WAIT_BUSY`状态，等待转换完成。

`BUSY`拉低后依次进入`READ_CH1`至`READ_CH4`状态，完成读取后进入`READ_STOP`状态，发出读取完成信号后回到`IDLE`状态，等待下一次触发。

```verilog
`timescale 1ns / 1ps

module ad7606_4 (
  input  clk,
  input  rst,
  input [15:0] data_in,  //ad7606通道a输入并行读取数据
  input  ad_busy,  //ad7606输入busy信号
  input  capture_flag, //外界输入开始数据采集的标志

output reg ad_cs,   //读ad7606的使能信号
  output reg ad_rd,   //读ad7606的时钟信号
  output reg ad_convstab, //ad7606开始转换信号,低电平有效
  output reg ad_reset,  //ad7606复位信号

output reg [15:0] data_ch1,
  output reg [15:0] data_ch2,
  output reg [15:0] data_ch3,
  output reg [15:0] data_ch4,

output wire capture_over
);

localparam RESET = 10'b0_000_000_001;
  localparam IDLE = 10'b0_000_000_010;
  localparam AD_CONV = 10'b0_000_000_100;
  localparam WAIT_1 = 10'b0_000_001_000;
  localparam WAIT_BUSY = 10'b0_000_010_000;
  localparam READ_CH1 = 10'b0_000_100_000;
  localparam READ_CH2 = 10'b0_001_000_000;
  localparam READ_CH3 = 10'b0_010_000_000;
  localparam READ_CH4 = 10'b0_100_000_000;
  localparam READ_STOP = 10'b1_000_000_000;

localparam RESET_TIME = 5; //reset高电平持续时间
  localparam CONV_TIME = 5;//AD_CONV状态持续时间等价转换信号低电平持续时间
  localparam WAIT_TIME = 5;//WAIT_1状态持续时间
  localparam FIV_CLK = 2;

reg [9:0] state;
  reg [5:0] cnt;//在数据读取状态表示分频系数

reg [2 : 0] over;

always @(posedge clk)
  if (!rst) cnt <= 'd0;
  else if (state == RESET)
    if (cnt == RESET_TIME) cnt <= 'd0;
    else cnt <= cnt + 1;
  else if (state == AD_CONV)
    if (cnt == CONV_TIME) cnt <= 'd0;
    else cnt <= cnt + 1;
  else if (state == WAIT_1)
    if (cnt == WAIT_TIME) cnt <= 'd0;
    else cnt <= cnt + 1;
  else if (state == WAIT_BUSY)
    if (ad_busy == 1'b0) cnt <= 'd0;
    else cnt <= cnt;
  else if (state == READ_CH1 || state == READ_CH2 || state == READ_CH3 || state == READ_CH4)
    if (cnt == (2 * FIV_CLK - 1)) cnt <= 'd0;
    else cnt <= cnt + 1;

// verilog_format: off// else statement auto format error
  always @(posedge clk)
  if (!rst) state <= RESET;
  else begin
    case (state)
      RESET: if (cnt == RESET_TIME) state <= IDLE;
         else state <= RESET;
      IDLE:  if (capture_flag == 1'b1) state <= AD_CONV;
         else state <= IDLE;
      AD_CONV: if (cnt == CONV_TIME) state <= WAIT_1;
         else state <= AD_CONV;
      WAIT_1:  if (cnt == WAIT_TIME) state <= WAIT_BUSY;
         else state <= WAIT_1;
      WAIT_BUSY: if (ad_busy == 1'b0) state <= READ_CH1;
         else state <= WAIT_BUSY;
      READ_CH1:if (cnt == (2 * FIV_CLK - 1)) state <= READ_CH2;
         else state <= READ_CH1;
      READ_CH2:if (cnt == (2 * FIV_CLK - 1)) state <= READ_CH3;
         else state <= READ_CH2;
      READ_CH3:if (cnt == (2 * FIV_CLK - 1)) state <= READ_CH4;
         else state <= READ_CH3;
      READ_CH4:if (cnt == (2 * FIV_CLK - 1)) state <= READ_STOP;
         else state <= READ_CH4;
      READ_STOP: state <= IDLE;
      default: state <= IDLE;
    endcase
  end
// verilog_format: on

//输出信号
  always @(posedge clk)
  if (!rst) ad_convstab <= 1'b1;
  else if (state == AD_CONV) ad_convstab <= 1'b0;
  else ad_convstab <= 1'b1;

always @(posedge clk)
  if (!rst) ad_cs <= 1'b1;
  else if (state == WAIT_BUSY && ad_busy == 1'b0) ad_cs <= 1'b0;
  else if (state == READ_STOP) ad_cs <= 1'b1;
  else ad_cs <= ad_cs;
  
  always @(posedge clk)
  if (!rst) ad_rd <= 1'b1;
  else if (state == READ_CH1 || state == READ_CH2 || state == READ_CH3 || state == READ_CH4)
    if (cnt == (FIV_CLK - 1)) ad_rd <= 1'b0;
    else if (cnt == 2 * FIV_CLK - 1) ad_rd <= 1'b1;
    else ad_rd <= ad_rd;
  else ad_rd <= 1'b1;

//ad7606复位
  always @(posedge clk) begin
  if (!rst) ad_reset <= 1'd1;
  else begin
    if (state == RESET) ad_reset <= 1'd1;
    else ad_reset <= 1'd0;
  end
  end

//将采集到的数据存储到data_ch1-data_ch4中      
  always @(posedge clk)
  if (!rst) begin
    data_ch1 <= 16'd0;
    data_ch2 <= 16'd0;
    data_ch3 <= 16'd0;
    data_ch4 <= 16'd0;
  end else if (state == READ_CH1 && cnt == (2 * FIV_CLK - 1)) begin
    data_ch1 <= data_in;
  end else if (state == READ_CH2 && cnt == (2 * FIV_CLK - 1)) begin
    data_ch2 <= data_in;
  end else if (state == READ_CH3 && cnt == (2 * FIV_CLK - 1)) begin
    data_ch3 <= data_in;
  end else if (state == READ_CH4 && cnt == (2 * FIV_CLK - 1)) begin
    data_ch4 <= data_in;
  end else begin
    data_ch1 <= data_ch1;
    data_ch2 <= data_ch2;
    data_ch3 <= data_ch3;
    data_ch4 <= data_ch4;
  end

//4个通道采集结束后，对over信号打拍处理，输出over_flag
  assign capture_over = over[2];
  always @(posedge clk)
  if (!rst) over <= 3'd0;
  else if (state == READ_STOP) begin
    over[0] <= 1'b1;
    over[1] <= over[0];
    over[2] <= over[1];
  end else begin
    over[0] <= 1'b0;
    over[1] <= over[0];
    over[2] <= over[1];
  end

endmodule
```

### 仿真测试

按照时序图编写测试激励如下:

```verilog
`timescale 1ns / 1ps

module ad7606_4_tb ();

localparam N = 2000;

reg clk = 0, rst = 0, ad_busy = 0, capture_flag = 0;
  reg [15:0] data_sin  [N - 1:0];
  reg [15:0] data_cos  [N - 1:0];
  reg [15:0] data_in = 0;
  reg [ 1:0] cnt = 0;

wire ad_cs, ad_rd, ad_convstab, capture_over, ad_reset;
  wire [15:0] data_ch1, data_ch2, data_ch3, data_ch4;

integer i = 0;

initial begin
  $readmemh("../../matlab/sin.txt", data_sin);
  $readmemh("../../matlab/cos.txt", data_cos);
  #50 rst <= 1;
  #10000000 $stop;
  end

always begin
  #10 clk <= ~clk;
  end

always begin
  #40 capture_flag = 0;
  #4960 capture_flag = 1;
  end

always @(posedge ad_convstab) begin
  if (~ad_reset) begin
    #40 ad_busy = 1;
    #2000 ad_busy = 0;
  end
  else begin
    ad_busy = 0;
  end
  end

always @(negedge ad_rd) begin
  case (cnt)
    3'd0: data_in <= data_sin<i>;
    3'd1: data_in <= data_cos<i>;
    3'd2: data_in <= 0;
    3'd3: begin
      data_in <= 0;
      if (i == N - 1) begin
      i <= 0;
      end else i <= i + 1;
    end
  endcase
  cnt <= cnt + 1;
  end

ad7606_4 u_ad7606_4 (
  .clk   (clk),
  .rst   (rst),
  .data_in (data_in),
  .ad_busy (ad_busy),
  .capture_flag(capture_flag),
  .ad_cs   (ad_cs),
  .ad_rd   (ad_rd),
  .ad_convstab (ad_convstab),
  .ad_reset  (ad_reset),
  .data_ch1  (data_ch1),
  .data_ch2  (data_ch2),
  .data_ch3  (data_ch3),
  .data_ch4  (data_ch4),
  .capture_over(capture_over)
  );

endmodule
```

其中1/2通道为模拟的两路sin/cos信号，3/4通道输入为0。生成测试波形的matlab脚本如下:

```matlab
N = 2000;
n = 1:N;

x = fix((2^15 - 1) * sin(2*pi*n/N));
y = fix((2^15 - 1) * cos(2*pi*n/N));

fid1 = fopen('sin.txt','wt');
fid2 = fopen('cos.txt','wt');
for i = 1:N
fprintf(fid1,'%s\n',dec2hex(x(i),4));
fprintf(fid2,'%s\n',dec2hex(y(i),4));
end
fclose(fid1);
fclose(fid2);
```

仿真波形正常，正确读取到输入信号。

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单次读取的时序与数据手册相符。

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## 2. AD7606实物模拟

由于疫情原因提前回家，没有条件进行旋变的实物测试。目前手头还有一块ZYNQ可以模拟传感器的输入输出，使用ZYNQ7010的PL部分模拟AD7606的时序输出正弦信号进行测试。

### 程序编写

时序与上述介绍相同，不再赘述，代码如下：

```verilog
`timescale 1ns / 1ps

module ad7606_sim (
  input     clk,
  output reg [15:0] data_out,//ad7606通道a输出并行读取数据
  output reg  ad_busy, //ad7606输出busy信号

input ad_cs,  //读ad7606的使能信号
  input ad_rd,  //读ad7606的时钟信号
  input ad_convstab,//ad7606开始转换信号,低电平有效
  input ad_reset, //ad7606复位信号

input [15:0] data_ch1,
  input [15:0] data_ch2,
  input [15:0] data_ch3,
  input [15:0] data_ch4
);

localparam RESET = 9'b000_000_001;
  localparam IDLE = 9'b000_000_010;
  localparam AD_CONV = 9'b000_000_100;
  localparam AD_EN = 9'b000_001_000;
  localparam WRITE_CH1 = 9'b000_010_000;
  localparam WRITE_CH2 = 9'b000_100_000;
  localparam WRITE_CH3 = 9'b001_000_000;
  localparam WRITE_CH4 = 9'b010_000_000;
  localparam WRITE_STOP = 9'b100_000_000;

localparam CONV_TIME = 200;//AD_CONV状态持续时间
  reg [ 7:0] cnt;
  reg [ 8:0] state;
  reg [15:0] data_buf[3:0];
  reg [ 1:0] ad_rd_buf;

//读取时钟缓存
  always @(posedge clk) begin
  if (ad_reset) begin
    ad_rd_buf <= 2'b11;
  end else begin
    ad_rd_buf <= {ad_rd_buf[0], ad_rd};
  end
  end

//数据缓存
  integer i;
  always @(posedge clk) begin
  if (ad_reset) begin
    for (i = 0; i < 4; i = i + 1) begin
      data_buf<i> <= 16'b0;
    end
  end else begin
    if (state == IDLE) begin
      data_buf[0] <= data_ch1;
      data_buf[1] <= data_ch2;
      data_buf[2] <= data_ch3;
      data_buf[3] <= data_ch4;
    end else begin
      for (i = 0; i < 4; i = i + 1) begin
      data_buf<i> <= data_buf<i>;
      end
    end
  end
  end

//计数器模拟转换过程busy信号
  always @(posedge clk) begin
  if (ad_reset) begin
    cnt <= 8'd0;
  end else begin
    case (state)
      AD_CONV: begin
      if (cnt == CONV_TIME - 1'b1) begin
        cnt <= 8'd0;
      end else begin
        cnt <= cnt + 1'd1;
      end
      end
      default: begin
      cnt <= 8'd0;
      end
    endcase
  end
  end

always @(posedge clk) begin
  if (ad_reset) begin
    ad_busy <= 1'b0;
  end else begin
    if (state == AD_CONV) begin
      ad_busy <= 1'b1;
    end else begin
      ad_busy <= 1'b0;
    end
  end
  end

//数据输出
  always @(posedge clk) begin
  if (ad_reset) begin
    data_out <= 16'b0;
  end else begin
    case (state)
      WRITE_CH1: begin
      if (ad_rd_buf == 2'b10) begin
        data_out <= data_buf[0];
      end else begin
        data_out <= data_out;
      end
      end
      WRITE_CH2: begin
      if (ad_rd_buf == 2'b10) begin
        data_out <= data_buf[1];
      end else begin
        data_out <= data_out;
      end
      end
      WRITE_CH3: begin
      if (ad_rd_buf == 2'b10) begin
        data_out <= data_buf[2];
      end else begin
        data_out <= data_out;
      end
      end
      WRITE_CH4: begin
      if (ad_rd_buf == 2'b10) begin
        data_out <= data_buf[3];
      end else begin
        data_out <= data_out;
      end
      end
      default: begin
      data_out <= 16'b0;
      end
    endcase
  end
  end

//状态机切换
  always @(posedge clk) begin
  if (ad_reset) begin
    state <= RESET;
  end else begin
    case (state)
      RESET: begin
      state <= IDLE;
      end
      IDLE: begin
      if (~ad_convstab) begin
        state <= AD_CONV;
      end else begin
        state <= IDLE;
      end
      end
      AD_CONV: begin
      if (cnt == CONV_TIME - 1'b1) begin
        state <= AD_EN;
      end else begin
        state <= AD_CONV;
      end
      end
      AD_EN: begin
      if (~ad_cs) begin
        state <= WRITE_CH1;
      end else begin
        state <= AD_EN;
      end
      end
      WRITE_CH1: begin
      if (ad_rd_buf == 2'b01) begin
        state <= WRITE_CH2;
      end else begin
        state <= WRITE_CH1;
      end
      end
      WRITE_CH2: begin
      if (ad_rd_buf == 2'b01) begin
        state <= WRITE_CH3;
      end else begin
        state <= WRITE_CH2;
      end
      end
      WRITE_CH3: begin
      if (ad_rd_buf == 2'b01) begin
        state <= WRITE_CH4;
      end else begin
        state <= WRITE_CH3;
      end
      end
      WRITE_CH4: begin
      if (ad_rd_buf == 2'b01) begin
        state <= WRITE_STOP;
      end else begin
        state <= WRITE_CH4;
      end
      end
      WRITE_STOP: begin
      state <= IDLE;
      end
      default: state <= IDLE;
    endcase
  end
  end

endmodule
```

ZYNQ使用Vivado进行开发，支持Block Design，可以轻松地添加各种Xilinx提供及客户自行编写的IP核。使用Block Design添加DDS及Clock Wizard模块，完成顶层模块的编写。

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完成连线后点击Generate Block Design生成IP核，再点击Create HDL Wrapper生成HDL包装文件，以便后续的仿真与综合使用。

### 仿真测试

将驱动及AD7606仿真模块的对应端口连接，编写测试激励如下：

```verilog
`timescale 1ns / 1ps

module top_tb;

reg clk_50m = 0, rst = 0, capture_flag = 0;

wire ad_busy, ad_cs, ad_rd, ad_convstab, capture_over, ad_reset;
  wire [15:0] data_ch1, data_ch2, data_ch3, data_ch4, data_out;

initial begin
  #50 rst <= 1;
  #200000 $stop;
  end

always begin
  #10 clk_50m <= ~clk_50m;
  end

always begin
  #40 capture_flag = 0;
  #4960 capture_flag = 1;
  end

ad7606_4 u_ad7606_4 (
  .clk   (clk_50m),
  .rst   (rst),
  .data_in (data_out),
  .ad_busy (ad_busy),
  .capture_flag(capture_flag),
  .ad_cs   (ad_cs),
  .ad_rd   (ad_rd),
  .ad_convstab (ad_convstab),
  .ad_reset  (ad_reset),
  .data_ch1  (data_ch1),
  .data_ch2  (data_ch2),
  .data_ch3  (data_ch3),
  .data_ch4  (data_ch4),
  .capture_over(capture_over)
  );

top_wrapper u_top_wrapper (
  .ad_busy_0  (ad_busy),
  .ad_convstab_0(ad_convstab),
  .ad_cs_0  (ad_cs),
  .ad_rd_0  (ad_rd),
  .ad_reset (ad_reset),
  .clk_in1  (clk_50m),
  .data_out_0 (data_out)
  );

endmodule
```

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仿真波形正常。

### 实物测试

将两块开发板按对应引脚连接后，分别烧写程序，使用片上逻辑分析仪观察信号，信号读取正常。

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lugl4313820

非常牛的帖子，感谢分享！

yyliu

请教下，硬件如何连接。AD7606是开发板资源吗，还是通过排针IO引脚去驱动AD7606

Jimmy_Arareb

本帖最后由 Jimmy_Arareb 于 2023-1-16 16:38 编辑

yyliu 发表于 2023-1-16 09:19 请教下，硬件如何连接。AD7606是开发板资源吗，还是通过排针IO引脚去驱动AD7606

不是开发板上的，是外接的。其实想给正点原子提点小建议，开发板两侧的排针只有边上有地线，在连接并口外设的时候容易串扰，希望以后的fpga开发板引出的排针能每隔几个io加一个地，保证信号完整性。

另外我现在手头没有ad7606，是拿另一块fpga模拟ad7606的时序。

【国产FPGA 正点原子DFPGL22G开发板】三、 AD7606驱动编写 [复制链接]

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